CHOI, Y. (1990). Design of self-testable wafer-scale processor arrays. International journal of electronics, 69(5), 665-671. https://doi.org/10.1080/00207219008920353
Citace podle Chicago (17th ed.)CHOI, YOON-HWA. "Design of Self-testable Wafer-scale Processor Arrays." International Journal of Electronics 69, no. 5 (1990): 665-671. https://doi.org/10.1080/00207219008920353.
Citace podle MLA (9th ed.)CHOI, YOON-HWA. "Design of Self-testable Wafer-scale Processor Arrays." International Journal of Electronics, vol. 69, no. 5, 1990, pp. 665-671, https://doi.org/10.1080/00207219008920353.
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