A new approach to the Population-Based Incremental Learning algorithm using virtual regions for task mapping on NoCs
Network-On-Chip (NoC) platforms were proposed to increase system performance in current and future generations of Multi-Processor System-on-Chip ranging from a few cores to hundreds. For such platforms, efficient mechanisms to perform the mapping of executable tasks are required in order to improve...
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| Vydáno v: | Journal of systems architecture Ročník 97; s. 443 - 454 |
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| Hlavní autoři: | , , |
| Médium: | Journal Article |
| Jazyk: | angličtina |
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Elsevier B.V
01.08.2019
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| ISSN: | 1383-7621, 1873-6165 |
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| Abstract | Network-On-Chip (NoC) platforms were proposed to increase system performance in current and future generations of Multi-Processor System-on-Chip ranging from a few cores to hundreds. For such platforms, efficient mechanisms to perform the mapping of executable tasks are required in order to improve metrics such as execution time, latency, energy, and others. The Population-Based Incremental Learning (PBIL) algorithm has been used as an optimization technique for the mapping of tasks onto the cores of NoC platforms. However, it does not scale well in terms of latency and other relevant metrics when the size of the platform and the number of tasks are increased. In this work, we propose a new approach, that relies on the PBIL algorithm, for the mapping of tasks called Virtual Regions PBIL (VRPBIL-NoC). This strategy consists of dividing the platform into virtual regions in order to improve the search of quality solutions. We evaluate the performance of our technique by comparing it against a set of heuristic techniques available in the literature, using an extended version of a well-known state-of-the-art simulator called Noxim. The results demonstrated that our approach can deliver better solutions compared to those provided by the other techniques in NoCs for varied configurations. |
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| AbstractList | Network-On-Chip (NoC) platforms were proposed to increase system performance in current and future generations of Multi-Processor System-on-Chip ranging from a few cores to hundreds. For such platforms, efficient mechanisms to perform the mapping of executable tasks are required in order to improve metrics such as execution time, latency, energy, and others. The Population-Based Incremental Learning (PBIL) algorithm has been used as an optimization technique for the mapping of tasks onto the cores of NoC platforms. However, it does not scale well in terms of latency and other relevant metrics when the size of the platform and the number of tasks are increased. In this work, we propose a new approach, that relies on the PBIL algorithm, for the mapping of tasks called Virtual Regions PBIL (VRPBIL-NoC). This strategy consists of dividing the platform into virtual regions in order to improve the search of quality solutions. We evaluate the performance of our technique by comparing it against a set of heuristic techniques available in the literature, using an extended version of a well-known state-of-the-art simulator called Noxim. The results demonstrated that our approach can deliver better solutions compared to those provided by the other techniques in NoCs for varied configurations. |
| Author | Bagherzadeh, N. García Morales, L.G. Aedo Cobo, J.E. |
| Author_xml | – sequence: 1 givenname: L.G. surname: García Morales fullname: García Morales, L.G. email: german.garcia@udea.edu.co organization: Department of Electronic Engineering, University of Antioquia, Medellín, Colombia – sequence: 2 givenname: J.E. surname: Aedo Cobo fullname: Aedo Cobo, J.E. email: jose.aedo@udea.edu.co organization: Department of Electronic Engineering, University of Antioquia, Medellín, Colombia – sequence: 3 givenname: N. surname: Bagherzadeh fullname: Bagherzadeh, N. email: nader@uci.edu organization: Department of Electrical Engineering and Computer Science, University of California, Irvine, USA |
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| Cites_doi | 10.1016/j.procs.2010.04.113 10.1016/j.sysarc.2018.10.001 10.1016/j.sysarc.2015.06.001 10.1016/j.sysarc.2012.10.004 10.1016/j.sysarc.2013.04.009 10.1109/MDT.2010.106 10.1109/TVLSI.2011.2159280 10.1049/iet-cdt.2010.0097 10.1145/2953878 10.1016/j.sysarc.2017.07.004 10.1016/j.sysarc.2017.01.008 10.1016/j.sysarc.2018.08.007 10.1016/j.sysarc.2010.04.007 10.1016/j.sysarc.2017.05.002 |
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| Copyright | 2019 Elsevier B.V. |
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| Keywords | Task mapping Multi-Processor system-on-Chip Network-on-Chip Multi-Applications Population-Based Incremental Learning |
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| References | Wang, Zhu, Jiang, Qiu, Wang (bib0023) 2017; 79 Bolanos, Aedo, Rivera, Bagherzadeh (bib0006) 2012; 18 Liu, Wei, Hu, Xu, Ouyang (bib0024) 2018; 90 Hamedani, Hessabi, Sarbazi-azad, Jerger (bib0018) 2012 Jiang, Balfour, Becker, Towles, Dally, Michelogiannakis, Kim (bib0026) 2013 Moréac, Rossi, Laurent, Bomel (bib0029) 2017; 77 Catania, Mineo, Monteleone, Palesi, Patti (bib0025) 2016; 27 Hosseinabady, Nunez-Yanez (bib0017) 2012; 6 Bolanos, Rivera, Aedo, Bagherzadeh (bib0019) 2013; 59 Hu, Marculescu (bib0003) 2004; volume 1 Carvalho, Calazans, Moraes (bib0005) 2010; 27 Singh, Wu, Kumar, Srikanthan (bib0008) 2010; 1 Garey, Johnson (bib0009) 1990 Li, Pan (bib0021) 2015 Sacanamboy, Quesada, Bolanos, Bernal, O’Sullivan (bib0036) 2017 He, Dong, Jang, Member, Bian, Pan, Member (bib0016) 2012; 20 Raina, Muthukumar (bib0007) 2009 Benini, De Micheli (bib0002) 2002 Fernandez-Alonso, Castells-Rufas, Joven, Carrabina (bib0004) 2012; 9 Kaushik, Kumar, Jigang, Srikanthan (bib0014) 2011 Chatterjee, Paul, Mukherjee, Chattopadhyay (bib0022) 2017; 74 Dick, Rhodes, Wolf (bib0033) 1998 Maqsood, Ali, Malik, Madani (bib0011) 2015; 61 Singh, Srikanthan, Kumar, Jigang (bib0013) 2010; 56 Abad, Prieto, Menezo, Colaso, Puente, Gregorio (bib0028) 2012 Ben-Itzhak, Zahavi, Cidon, Kolodny (bib0027) 2012 Racu, Indrusiak (bib0034) 2012 Baluja (bib0035) 1994 Mandelli, Ost, Carara, Guindani, Gouvea, Medeiros, Moraes (bib0012) 2011 Huang, Buckl, Raabe, Knoll (bib0015) 2011 Atitallah, Niar, Greiner, Meftali, Dekeyser (bib0032) 2006 Fattah, Rahmani, Xu, Kanduri, Liljeberg, Plosila, Tenhunen (bib0020) 2014 Sahu, Chattopadhyay (bib0010) 2013; 59 Kadri, Koudil (bib0031) 2019; 92 Asanovic, Catanzaro, Patterson, Yelick (bib0001) 2006; volume 19 García Morales, Aedo, Bagherzadeh (bib0030) 2018 Dick (10.1016/j.sysarc.2019.01.013_sbref0033) 1998 Garey (10.1016/j.sysarc.2019.01.013_bib0009) 1990 Bolanos (10.1016/j.sysarc.2019.01.013_bib0006) 2012; 18 Maqsood (10.1016/j.sysarc.2019.01.013_bib0011) 2015; 61 García Morales (10.1016/j.sysarc.2019.01.013_sbref0030) 2018 Jiang (10.1016/j.sysarc.2019.01.013_sbref0026) 2013 Sacanamboy (10.1016/j.sysarc.2019.01.013_sbref0036) 2017 Li (10.1016/j.sysarc.2019.01.013_bib0021) 2015 Hamedani (10.1016/j.sysarc.2019.01.013_sbref0018) 2012 Bolanos (10.1016/j.sysarc.2019.01.013_bib0019) 2013; 59 Catania (10.1016/j.sysarc.2019.01.013_bib0025) 2016; 27 Baluja (10.1016/j.sysarc.2019.01.013_bib0035) 1994 Chatterjee (10.1016/j.sysarc.2019.01.013_bib0022) 2017; 74 Singh (10.1016/j.sysarc.2019.01.013_bib0008) 2010; 1 Wang (10.1016/j.sysarc.2019.01.013_bib0023) 2017; 79 Sahu (10.1016/j.sysarc.2019.01.013_bib0010) 2013; 59 Fattah (10.1016/j.sysarc.2019.01.013_sbref0020) 2014 Benini (10.1016/j.sysarc.2019.01.013_sbref0002) 2002 Ben-Itzhak (10.1016/j.sysarc.2019.01.013_sbref0027) 2012 Singh (10.1016/j.sysarc.2019.01.013_bib0013) 2010; 56 Raina (10.1016/j.sysarc.2019.01.013_sbref0007) 2009 Kaushik (10.1016/j.sysarc.2019.01.013_sbref0014) 2011 Moréac (10.1016/j.sysarc.2019.01.013_bib0029) 2017; 77 Racu (10.1016/j.sysarc.2019.01.013_sbref0034) 2012 Liu (10.1016/j.sysarc.2019.01.013_bib0024) 2018; 90 Carvalho (10.1016/j.sysarc.2019.01.013_bib0005) 2010; 27 He (10.1016/j.sysarc.2019.01.013_bib0016) 2012; 20 Atitallah (10.1016/j.sysarc.2019.01.013_sbref0032) 2006 Asanovic (10.1016/j.sysarc.2019.01.013_sbref0001) 2006; volume 19 Huang (10.1016/j.sysarc.2019.01.013_sbref0015) 2011 Fernandez-Alonso (10.1016/j.sysarc.2019.01.013_bib0004) 2012; 9 Hosseinabady (10.1016/j.sysarc.2019.01.013_bib0017) 2012; 6 Hu (10.1016/j.sysarc.2019.01.013_sbref0003) 2004; volume 1 Mandelli (10.1016/j.sysarc.2019.01.013_sbref0012) 2011 Abad (10.1016/j.sysarc.2019.01.013_sbref0028) 2012 Kadri (10.1016/j.sysarc.2019.01.013_bib0031) 2019; 92 |
| References_xml | – volume: 56 start-page: 242 year: 2010 end-page: 255 ident: bib0013 article-title: Communication-aware heuristics for run-time task mapping on NoC-based MPSoC platforms publication-title: J. Syst. Archit. – start-page: 877 year: 2009 end-page: 882 ident: bib0007 article-title: Traffic aware scheduling algorithm for network on chip publication-title: 2009 6th International Conference on Information Technology: New Generations – start-page: 203 year: 2011 end-page: 207 ident: bib0014 article-title: Run-time computation and communication aware mapping heuristic for NoC-based heterogeneous MPSoC platforms publication-title: Fourth International Symposium on Parallel Architectures, Algorithms and Programming, IEEE – volume: 79 start-page: 59 year: 2017 end-page: 72 ident: bib0023 article-title: Dynamic application allocation with resource balancing on NoC based many-core embedded systems publication-title: J. Syst. Archit. – volume: 27 start-page: 1 year: 2016 end-page: 25 ident: bib0025 article-title: Cycle-accurate network on chip simulation with Noxim publication-title: ACM Trans. Model. Comput. Simul. – volume: 1 start-page: 1019 year: 2010 end-page: 1026 ident: bib0008 article-title: Run-time mapping of multiple communicating tasks on MPSoC platforms publication-title: Procedia Comput. Sci. – volume: 59 start-page: 60 year: 2013 end-page: 76 ident: bib0010 article-title: A survey on application mapping strategies for network-on-chip design publication-title: J. Syst. Archit. – start-page: 458 year: 2014 end-page: 465 ident: bib0020 article-title: Mixed-criticality run-time task mapping for NoC-based many-core systems publication-title: 2014 22nd Euromicro International Conference on Parallel, Distributed, and Network-Based Processing – year: 2012 ident: bib0018 article-title: Exploration of temperature constraints for thermal aware mapping of 3d networks on chip publication-title: 2012 20th Euromicro International Conference on Parallel, Distributed and Network-based Processing – start-page: 9 year: 2015 end-page: 16 ident: bib0021 article-title: A fast and energy efficient branch and bound algorithm for NoC task mapping publication-title: 2015 33rd IEEE International Conference on Computer Design (ICCD) (61204030) – start-page: 99 year: 2012 end-page: 106 ident: bib0028 article-title: TOPAZ: an open-source interconnection network simulator for chip multiprocessors and supercomputers publication-title: Proceedings of the 2012 6th IEEE/ACM International Symposium on Networks-on-Chip, NoCS 2012 – start-page: 447 year: 2011 end-page: 454 ident: bib0015 article-title: Energy-aware task allocation for network-on-chip based heterogeneous multiprocessor systems publication-title: 2011 19th International Euromicro Conference on Parallel, Distributed and Network-Based Processing – start-page: 51 year: 2012 end-page: 57 ident: bib0027 article-title: HNOCS: modular open-source simulator for heterogeneous NoCs, publication-title: Proceedings - 2012 International Conference on Embedded Computer Systems: Architectures, Modeling and Simulation, IC-SAMOS 2012 – volume: 74 start-page: 61 year: 2017 end-page: 77 ident: bib0022 article-title: Deadline and energy aware dynamic task mapping and scheduling for network-on-chip based multi-core platform publication-title: J. Syst. Archit. – volume: volume 1 start-page: 1 year: 2004 end-page: 5 ident: bib0003 article-title: Energy-aware communication and task scheduling for network-on-chip architectures under real-time constraints publication-title: Proceedings Design, Automation and Test in Europe Conference and Exhibition – start-page: 298 year: 2006 end-page: 310 ident: bib0032 article-title: Estimating energy consumption for an MPSoc architectural exploration publication-title: Proceedings of the 19th international conference on Architecture of Computing Systems – start-page: 97 year: 1998 end-page: 101 ident: bib0033 article-title: TGFF: task graphs for free publication-title: Proceedings of the Sixth International Workshop on Hardware/Software Codesign. (CODES/CASHE’98) – volume: 77 start-page: 112 year: 2017 end-page: 124 ident: bib0029 article-title: Bit-accurate energy estimation for networks-on-chip publication-title: J. Syst. Archit. – volume: 9 start-page: 22 year: 2012 end-page: 32 ident: bib0004 article-title: Survey of NoC and programming models proposals for MPSoC publication-title: Int. J. Comput. Sci. Issues – volume: 92 start-page: 39 year: 2019 end-page: 52 ident: bib0031 article-title: A survey on fault-tolerant application mapping techniques for network-on-chip publication-title: J. Syst. Archit. – volume: 59 start-page: 429 year: 2013 end-page: 440 ident: bib0019 article-title: From UML specifications to mapping and scheduling of tasks into a NoC, with reliability considerations publication-title: J. Syst. Archit. – start-page: 622 year: 2018 end-page: 626 ident: bib0030 article-title: Simulation-based evaluation strategy for task mapping approaches in WNoC platforms publication-title: 26th Euromicro International Conference on Parallel, Distributed, and Network-Based Processing Simulation-Based, Cambridge,United Kingdom – volume: 61 start-page: 293 year: 2015 end-page: 306 ident: bib0011 article-title: Dynamic task mapping for network-on-chip based systems publication-title: J. Syst. Archit. – year: 1990 ident: bib0009 article-title: Computers and Intractability; a Guide to the Theory of NP-Completeness – year: 1994 ident: bib0035 publication-title: Population-Based Incremental Learning: a Method for Integrating Genetic Search Based Function Optimization and Competitive Learning, Tech. rep. – volume: 6 start-page: 1 year: 2012 end-page: 11 ident: bib0017 article-title: Run-time stochastic task mapping on a large scale network-on-chip with dynamically reconfigurable tiles publication-title: IET Comput. Digital Tech. – start-page: 1676 year: 2011 end-page: 1679 ident: bib0012 article-title: Energy-aware dynamic task mapping for NoC-based MPSoCs publication-title: Proceedings - IEEE International Symposium on Circuits and Systems – start-page: 938 year: 2017 end-page: 945 ident: bib0036 article-title: A comparison between two optimisation alternatives for mapping in wireless network on chip publication-title: Proceedings - 2016 IEEE 28th International Conference on Tools with Artificial Intelligence, ICTAI 2016 – start-page: 418 year: 2002 end-page: 419 ident: bib0002 article-title: Networks on chip: a new paradigm for systems on chip design publication-title: Proceedings -Design, Automation and Test in Europe, DATE – year: 2012 ident: bib0034 article-title: Using genetic algorithms to map hard real-time on NoC-based systems publication-title: ReCoSoC 2012 - 7th International Workshop on Reconfigurable and Communication-Centric Systems-on-Chip, Proceedings – volume: 20 start-page: 1496 year: 2012 end-page: 1509 ident: bib0016 article-title: UNISM : unified scheduling and mapping for general networks on chip publication-title: IEEE Trans. Very Large Scale Integr. (VLSI) Syst. – volume: volume 19 year: 2006 ident: bib0001 article-title: The landscape of parallel computing research: a view from berkeley publication-title: EECS Department University of California Berkeley Tech Rep. 18 – volume: 18 start-page: 901 year: 2012 end-page: 916 ident: bib0006 article-title: Mapping and scheduling in heterogeneous NoC through population-based incremental learning publication-title: J. Univ. Comput. Sci. – volume: 27 start-page: 26 year: 2010 end-page: 35 ident: bib0005 article-title: Dynamic task mapping for MPSoCs publication-title: IEEE Des. Test Comput. – start-page: 86 year: 2013 end-page: 96 ident: bib0026 article-title: A detailed and flexible cycle-accurate network-on-chip simulator publication-title: ISPASS 2013 - IEEE International Symposium on Performance Analysis of Systems and Software – volume: 90 start-page: 23 year: 2018 end-page: 33 ident: bib0024 article-title: Task scheduling with fault-tolerance in real-time heterogeneous systems publication-title: J. Syst. Archit. – volume: 1 start-page: 1019 issue: 1 year: 2010 ident: 10.1016/j.sysarc.2019.01.013_bib0008 article-title: Run-time mapping of multiple communicating tasks on MPSoC platforms publication-title: Procedia Comput. Sci. doi: 10.1016/j.procs.2010.04.113 – start-page: 622 year: 2018 ident: 10.1016/j.sysarc.2019.01.013_sbref0030 article-title: Simulation-based evaluation strategy for task mapping approaches in WNoC platforms – start-page: 458 year: 2014 ident: 10.1016/j.sysarc.2019.01.013_sbref0020 article-title: Mixed-criticality run-time task mapping for NoC-based many-core systems – start-page: 99 year: 2012 ident: 10.1016/j.sysarc.2019.01.013_sbref0028 article-title: TOPAZ: an open-source interconnection network simulator for chip multiprocessors and supercomputers – start-page: 298 year: 2006 ident: 10.1016/j.sysarc.2019.01.013_sbref0032 article-title: Estimating energy consumption for an MPSoc architectural exploration – year: 1994 ident: 10.1016/j.sysarc.2019.01.013_bib0035 – start-page: 97 year: 1998 ident: 10.1016/j.sysarc.2019.01.013_sbref0033 article-title: TGFF: task graphs for free – volume: 92 start-page: 39 issue: April 2018 year: 2019 ident: 10.1016/j.sysarc.2019.01.013_bib0031 article-title: A survey on fault-tolerant application mapping techniques for network-on-chip publication-title: J. Syst. Archit. doi: 10.1016/j.sysarc.2018.10.001 – volume: 9 start-page: 22 issue: 2 year: 2012 ident: 10.1016/j.sysarc.2019.01.013_bib0004 article-title: Survey of NoC and programming models proposals for MPSoC publication-title: Int. J. Comput. Sci. Issues – start-page: 877 year: 2009 ident: 10.1016/j.sysarc.2019.01.013_sbref0007 article-title: Traffic aware scheduling algorithm for network on chip – start-page: 86 year: 2013 ident: 10.1016/j.sysarc.2019.01.013_sbref0026 article-title: A detailed and flexible cycle-accurate network-on-chip simulator – volume: volume 1 start-page: 1 year: 2004 ident: 10.1016/j.sysarc.2019.01.013_sbref0003 article-title: Energy-aware communication and task scheduling for network-on-chip architectures under real-time constraints – year: 2012 ident: 10.1016/j.sysarc.2019.01.013_sbref0034 article-title: Using genetic algorithms to map hard real-time on NoC-based systems – volume: 61 start-page: 293 issue: 7 year: 2015 ident: 10.1016/j.sysarc.2019.01.013_bib0011 article-title: Dynamic task mapping for network-on-chip based systems publication-title: J. Syst. Archit. doi: 10.1016/j.sysarc.2015.06.001 – volume: 59 start-page: 60 issue: 1 year: 2013 ident: 10.1016/j.sysarc.2019.01.013_bib0010 article-title: A survey on application mapping strategies for network-on-chip design publication-title: J. Syst. Archit. doi: 10.1016/j.sysarc.2012.10.004 – start-page: 203 year: 2011 ident: 10.1016/j.sysarc.2019.01.013_sbref0014 article-title: Run-time computation and communication aware mapping heuristic for NoC-based heterogeneous MPSoC platforms – volume: 59 start-page: 429 issue: 7 year: 2013 ident: 10.1016/j.sysarc.2019.01.013_bib0019 article-title: From UML specifications to mapping and scheduling of tasks into a NoC, with reliability considerations publication-title: J. Syst. Archit. doi: 10.1016/j.sysarc.2013.04.009 – volume: 27 start-page: 26 issue: 5 year: 2010 ident: 10.1016/j.sysarc.2019.01.013_bib0005 article-title: Dynamic task mapping for MPSoCs publication-title: IEEE Des. Test Comput. doi: 10.1109/MDT.2010.106 – year: 2012 ident: 10.1016/j.sysarc.2019.01.013_sbref0018 article-title: Exploration of temperature constraints for thermal aware mapping of 3d networks on chip – start-page: 938 year: 2017 ident: 10.1016/j.sysarc.2019.01.013_sbref0036 article-title: A comparison between two optimisation alternatives for mapping in wireless network on chip – volume: 20 start-page: 1496 issue: 8 year: 2012 ident: 10.1016/j.sysarc.2019.01.013_bib0016 article-title: UNISM : unified scheduling and mapping for general networks on chip publication-title: IEEE Trans. Very Large Scale Integr. (VLSI) Syst. doi: 10.1109/TVLSI.2011.2159280 – volume: 6 start-page: 1 year: 2012 ident: 10.1016/j.sysarc.2019.01.013_bib0017 article-title: Run-time stochastic task mapping on a large scale network-on-chip with dynamically reconfigurable tiles publication-title: IET Comput. Digital Tech. doi: 10.1049/iet-cdt.2010.0097 – volume: 27 start-page: 1 issue: 1 year: 2016 ident: 10.1016/j.sysarc.2019.01.013_bib0025 article-title: Cycle-accurate network on chip simulation with Noxim publication-title: ACM Trans. Model. Comput. Simul. doi: 10.1145/2953878 – start-page: 418 year: 2002 ident: 10.1016/j.sysarc.2019.01.013_sbref0002 article-title: Networks on chip: a new paradigm for systems on chip design – start-page: 447 year: 2011 ident: 10.1016/j.sysarc.2019.01.013_sbref0015 article-title: Energy-aware task allocation for network-on-chip based heterogeneous multiprocessor systems – volume: 79 start-page: 59 year: 2017 ident: 10.1016/j.sysarc.2019.01.013_bib0023 article-title: Dynamic application allocation with resource balancing on NoC based many-core embedded systems publication-title: J. Syst. Archit. doi: 10.1016/j.sysarc.2017.07.004 – volume: 74 start-page: 61 year: 2017 ident: 10.1016/j.sysarc.2019.01.013_bib0022 article-title: Deadline and energy aware dynamic task mapping and scheduling for network-on-chip based multi-core platform publication-title: J. Syst. Archit. doi: 10.1016/j.sysarc.2017.01.008 – volume: 90 start-page: 23 issue: April year: 2018 ident: 10.1016/j.sysarc.2019.01.013_bib0024 article-title: Task scheduling with fault-tolerance in real-time heterogeneous systems publication-title: J. Syst. Archit. doi: 10.1016/j.sysarc.2018.08.007 – start-page: 9 year: 2015 ident: 10.1016/j.sysarc.2019.01.013_bib0021 article-title: A fast and energy efficient branch and bound algorithm for NoC task mapping – volume: volume 19 year: 2006 ident: 10.1016/j.sysarc.2019.01.013_sbref0001 article-title: The landscape of parallel computing research: a view from berkeley – volume: 56 start-page: 242 issue: 7 year: 2010 ident: 10.1016/j.sysarc.2019.01.013_bib0013 article-title: Communication-aware heuristics for run-time task mapping on NoC-based MPSoC platforms publication-title: J. Syst. Archit. doi: 10.1016/j.sysarc.2010.04.007 – start-page: 1676 year: 2011 ident: 10.1016/j.sysarc.2019.01.013_sbref0012 article-title: Energy-aware dynamic task mapping for NoC-based MPSoCs – volume: 77 start-page: 112 year: 2017 ident: 10.1016/j.sysarc.2019.01.013_bib0029 article-title: Bit-accurate energy estimation for networks-on-chip publication-title: J. Syst. Archit. doi: 10.1016/j.sysarc.2017.05.002 – year: 1990 ident: 10.1016/j.sysarc.2019.01.013_bib0009 – start-page: 51 year: 2012 ident: 10.1016/j.sysarc.2019.01.013_sbref0027 article-title: HNOCS: modular open-source simulator for heterogeneous NoCs, – volume: 18 start-page: 901 issue: 7 year: 2012 ident: 10.1016/j.sysarc.2019.01.013_bib0006 article-title: Mapping and scheduling in heterogeneous NoC through population-based incremental learning publication-title: J. Univ. Comput. Sci. |
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| Title | A new approach to the Population-Based Incremental Learning algorithm using virtual regions for task mapping on NoCs |
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