Access pattern-based high-performance main memory system for graph processing on single machines

With the increasing complexity of graph structures, the current real-world large-scale graphs are being represented by a considerable amount of vertex and edge data. Furthermore, the analysis of a large number of computing nodes has become a very complicated job that requires a large amount of hardw...

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Vydáno v:Future generation computer systems Ročník 108; s. 560 - 573
Hlavní autoři: Yun, Ji-Tae, Yoon, Su-Kyung, Kim, Jeong-Geun, Kim, Shin-Dug
Médium: Journal Article
Jazyk:angličtina
Vydáno: Elsevier B.V 01.07.2020
Témata:
Buffer management
Machine learning
Main memory
Prefetching
Buffer management
Main memory
Prefetching
Machine learning
ISSN:0167-739X
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Shrnutí:With the increasing complexity of graph structures, the current real-world large-scale graphs are being represented by a considerable amount of vertex and edge data. Furthermore, the analysis of a large number of computing nodes has become a very complicated job that requires a large amount of hardware resources. Moreover, in large-scale graph processing, the vertex and edge data show random and sequential memory access patterns at the same time, and this is a major bottleneck in graph processing. In this paper, we present a high-capacity main memory system with an intelligent pattern-aware prefetching engine to overcome the scalability problem and the memory inefficiency of single-machine graph processing. The proposed intelligent pattern-aware prefetching engine is designed to predict and handle sequential or regular patterns and random-access patterns simultaneously. Experimental results demonstrated that the proposed model exhibited performance improvements of 60% over conventional DRAM models, approximately 40% over the existing prefetch models, and about 12.5% over the latest prefetch models. •We present a pattern-aware main memory to overcome scalability and inefficiency of single-machine graph processing.•This system is designed to predict and handle sequential-, regular-, and random-access patterns simultaneously.•We mitigate the performance degradation due to the complicated and irregular memory accesses of graph processing.
ISSN:0167-739X
DOI:10.1016/j.future.2020.03.015