A power optimization approach for mixed polarity Reed–Muller logic circuits based on multi-strategy fusion memetic algorithm

The power optimization of mixed polarity Reed–Muller (MPRM) logic circuits is a classic combinatorial optimization problem. Existing optimization approaches often suffer from slow convergence and a propensity to converge to local optima, limiting their effectiveness in achieving optimal power effici...

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Bibliographic Details
Published in:Frontiers of information technology & electronic engineering Vol. 26; no. 3; pp. 415 - 426
Main Authors: Zhang, Mengyu, He, Zhenxue, Wang, Yijin, Zhao, Xiaojun, Zhang, Xiaodan, Xiao, Limin, Wang, Xiang
Format: Journal Article
Language:English
Published: Hangzhou Zhejiang University Press 01.03.2025
Springer Nature B.V
Subjects:
Algorithms
Circuits
Combinatorial analysis
Communications Engineering
Computer Hardware
Computer Science
Computer Systems Organization and Communication Networks
Effectiveness
Electrical Engineering
Electronics and Microelectronics
Instrumentation
Logic circuits
Maximum power
Networks
Optimization
Optimization algorithms
Power efficiency
Research Article
Searching
Power optimization
组合优化问题
混合极性Reed–Muller(MPRM)
Mixed polarity Reed–Muller (MPRM)
多策略融合模因算法(MFMA)
TP331.1
Multi-strategy fusion memetic algorithm (MFMA)
Combinatorial optimization problem
功耗优化
ISSN:2095-9184, 2095-9230
Online Access:Get full text
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Summary:The power optimization of mixed polarity Reed–Muller (MPRM) logic circuits is a classic combinatorial optimization problem. Existing optimization approaches often suffer from slow convergence and a propensity to converge to local optima, limiting their effectiveness in achieving optimal power efficiency. First, we propose a novel multi-strategy fusion memetic algorithm (MFMA). MFMA integrates global exploration via the chimp optimization algorithm with local exploration using the coati optimization algorithm based on the optimal position learning and adaptive weight factor (COA-OLA), complemented by population management through truncation selection. Second, leveraging MFMA, we propose a power optimization approach for MPRM logic circuits that searches for the best polarity configuration to minimize circuit power. Experimental results based on Microelectronics Center of North Carolina (MCNC) benchmark circuits demonstrate significant improvements over existing power optimization approaches. MFMA achieves a maximum power saving rate of 72.30% and an average optimization rate of 43.37%; it searches for solutions faster and with higher quality, validating its effectiveness and superiority in power optimization.
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ISSN:2095-9184
2095-9230
DOI:10.1631/FITEE.2400513