Analog circuit sizing based on Evolutionary Algorithms and deep learning

The use of machine learning-based techniques has expanded to many areas that require optimization. One of such area is Integrated Circuit (IC) design and sizing optimization, where we propose a new framework that combines Deep Neural Networks (DNNs) and Evolutionary Algorithm (EA) for analog IC sizi...

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Bibliographic Details
Published in:Expert systems with applications Vol. 237; p. 121480
Main Authors: Lberni, Abdelaziz, Marktani, Malika Alami, Ahaitouf, Abdelaziz, Ahaitouf, Ali
Format: Journal Article
Language:English
Published: Elsevier Ltd 01.03.2024
Subjects:
Analog circuit design
Automated circuit design
Deep Neural Network
Evolutionary algorithm
Simulation-based optimization
Automated circuit design
Deep Neural Network
Simulation-based optimization
Evolutionary algorithm
Analog circuit design
ISSN:0957-4174, 1873-6793
Online Access:Get full text
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Summary:The use of machine learning-based techniques has expanded to many areas that require optimization. One of such area is Integrated Circuit (IC) design and sizing optimization, where we propose a new framework that combines Deep Neural Networks (DNNs) and Evolutionary Algorithm (EA) for analog IC sizing automation. Our optimization framework incorporates EA, numerical performance evaluation, and DNN models to optimize the analog circuit sizing process. The main steps of the proposed optimization procedure can be summarized as follows: Firstly, we use EA and numerical performance evaluation to increase efficiency and produce highly accurate results for global optimization. Secondly, we incorporate a local search to enhance the performance of global optimization, with DNN models being used to evaluate the performance of analog circuits during this phase. Lastly, we employ DNN model evaluations instead of numerical performance evaluation for ranking candidate designs, which significantly speeds up the local minimum search. These successive steps make our method original and stand out perfectly from existing procedures published in the literature. Our framework is deployed on industrial-scale circuits with strict design specifications. Experimental results demonstrate that it achieves better results and is two times faster in the design process compared to traditional global optimization methods that use sequential SPICE simulation calls for local optimization.
ISSN:0957-4174
1873-6793
DOI:10.1016/j.eswa.2023.121480