A 20k-Spin Ising Chip to Solve Combinatorial Optimization Problems With CMOS Annealing

In the near future, the ability to solve combinatorial optimization problems will be a key technique to enable the IoT era. A new computing architecture called Ising computing and implemented using CMOS circuits is proposed. This computing maps the problems to an Ising model, a model to express the...

Ausführliche Beschreibung

Gespeichert in:
Bibliographische Detailangaben
Veröffentlicht in:IEEE journal of solid-state circuits Jg. 51; H. 1; S. 303 - 309
Hauptverfasser: Yamaoka, Masanao, Yoshimura, Chihiro, Hayashi, Masato, Okuyama, Takuya, Aoki, Hidetaka, Mizuno, Hiroyuki
Format: Journal Article
Sprache:Englisch
Veröffentlicht: IEEE 01.01.2016
Schlagworte:
Annealing
Chips
Circuits
CMOS
CMOS annealing
CMOS integrated circuits
Combinatorial analysis
combinatorial optimization problem
Computation
Computational modeling
Computer architecture
Integrated circuit modeling
Ising computing
Ising model
natural computing
Optimization
Semiconductor device modeling
SRAM
variation
Ising computing
combinatorial optimization problem
Ising model
natural computing
CMOS annealing
SRAM
variation
ISSN:0018-9200, 1558-173X
Online-Zugang:Volltext
Tags: Tag hinzufügen
Keine Tags, Fügen Sie den ersten Tag hinzu!
Beschreibung
Zusammenfassung:In the near future, the ability to solve combinatorial optimization problems will be a key technique to enable the IoT era. A new computing architecture called Ising computing and implemented using CMOS circuits is proposed. This computing maps the problems to an Ising model, a model to express the behavior of magnetic spins, and solves combinatorial optimization problems efficiently exploiting its intrinsic convergence properties. In the computing, "CMOS annealing" is used to find a better solution for the problems. A 20k-spin prototype Ising chip is fabricated in 65 nm process. The Ising chip achieves 100 MHz operation and its capability of solving combinatorial optimization problems using an Ising model is confirmed. The power efficiency of the chip can be estimated to be 1800 times higher than that of a general purpose CPU when running an approximation algorithm.
Bibliographie:ObjectType-Article-1
SourceType-Scholarly Journals-1
ObjectType-Feature-2
content type line 23
ISSN:0018-9200
1558-173X
DOI:10.1109/JSSC.2015.2498601