A 20k-Spin Ising Chip to Solve Combinatorial Optimization Problems With CMOS Annealing

In the near future, the ability to solve combinatorial optimization problems will be a key technique to enable the IoT era. A new computing architecture called Ising computing and implemented using CMOS circuits is proposed. This computing maps the problems to an Ising model, a model to express the...

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Veröffentlicht in:	IEEE journal of solid-state circuits Jg. 51; H. 1; S. 303 - 309
Hauptverfasser:	Yamaoka, Masanao, Yoshimura, Chihiro, Hayashi, Masato, Okuyama, Takuya, Aoki, Hidetaka, Mizuno, Hiroyuki
Format:	Journal Article
Sprache:	Englisch
Veröffentlicht:	IEEE 01.01.2016
Schlagworte:	Annealing Chips Circuits CMOS CMOS annealing CMOS integrated circuits Combinatorial analysis combinatorial optimization problem Computation Computational modeling Computer architecture Integrated circuit modeling Ising computing Ising model natural computing Optimization Semiconductor device modeling SRAM variation Ising computing combinatorial optimization problem Ising model natural computing CMOS annealing SRAM variation
ISSN:	0018-9200, 1558-173X
Online-Zugang:	Volltext
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