LSHIM: Low-Power and Small-Area Inexact Multiplier for High-Speed Error-Resilient Applications

Numerical computations in various applications can often tolerate a small degree of error. In fields such as data mining, encoding algorithms, image processing, machine learning, and signal processing where error resilience is crucial approximate computing can effectively replace precise computing t...

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Bibliographic Details
Published in:IEEE journal on emerging and selected topics in circuits and systems Vol. 15; no. 1; pp. 94 - 104
Main Authors: Izadi, Azin, Jamshidi, Vahid
Format: Journal Article
Language:English
Published: Piscataway IEEE 01.03.2025
The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subjects:
Accuracy
Adders
Algorithms
approximate computing
Approximate multiplier
Approximation algorithms
area
Arithmetic
Circuits
Computation
Data mining
Delay
Delays
Energy consumption
Image processing
Machine learning
Mitchell’s multiplication algorithm
Multiplication
Multipliers
Performance evaluation
Power consumption
Power demand
Resilience
Signal processing algorithms
ISSN:2156-3357, 2156-3365
Online Access:Get full text
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Summary:Numerical computations in various applications can often tolerate a small degree of error. In fields such as data mining, encoding algorithms, image processing, machine learning, and signal processing where error resilience is crucial approximate computing can effectively replace precise computing to minimize circuit delay and power consumption. In these contexts, a certain level of error is permissible. Multiplication, a fundamental arithmetic operation in computer systems, often leads to increased circuit delay, power usage, and area occupation when performed accurately by multipliers, which are key components in these applications. Thus, developing an optimal multiplier represents a significant advantage for inexact computing systems. In this paper, we introduce a novel approximate multiplier based on the Mitchell algorithm. The proposed design has been implemented using the Cadence software environment with the TSMC 45nm standard-cell library and a supply voltage of 1.1V. Simulation results demonstrate an average reduction of 31.7% in area, 46.8% in power consumption, and 36.1% in circuit delay compared to previous works. The mean relative error distance (MRED) for the proposed method is recorded at 2.6%.
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ISSN:2156-3357
2156-3365
DOI:10.1109/JETCAS.2024.3515055