Field‐programmable gate arrays and quantum Monte Carlo: Power efficient coprocessing for scalable high‐performance computing

Massively parallel architectures offer the potential to significantly accelerate an application relative to their serial counterparts. However, not all applications exhibit an adequate level of data and/or task parallelism to exploit such platforms. Furthermore, the power consumption associated with...

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Veröffentlicht in:International journal of quantum chemistry Jg. 119; H. 12
Hauptverfasser: Cardamone, Salvatore, Kimmitt, Jonathan R. R., Burton, Hugh G. A., Todman, Timothy J., Li, Shurui, Luk, Wayne, Thom, Alex J. W.
Format: Journal Article
Sprache:Englisch
Veröffentlicht: Hoboken, USA John Wiley & Sons, Inc 15.06.2019
Wiley Subscription Services, Inc
Schlagworte:
Chemistry
Computation
Computer simulation
Energy policy
Field programmable gate arrays
FPGA
Gate arrays
High performance computing
Performance enhancement
Physical chemistry
Platforms
Power consumption
Power measurement
quantum Monte Carlo
Quantum physics
variational Monte Carlo
ISSN:0020-7608, 1097-461X
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Zusammenfassung:Massively parallel architectures offer the potential to significantly accelerate an application relative to their serial counterparts. However, not all applications exhibit an adequate level of data and/or task parallelism to exploit such platforms. Furthermore, the power consumption associated with these forms of computation renders “scaling out” for exascale levels of performance incompatible with modern sustainable energy policies. In this work, we investigate the potential for field‐programmable gate arrays (FPGAs) to feature in future exascale platforms, and their capacity to improve performance per unit power measurements for the purposes of scientific computing. We have focused our efforts on variational Monte Carlo, and report on the benefits of coprocessing with a FPGA relative to a purely multicore system. Certain applications in quantum chemistry, such as quantum Monte Carlo, are particularly amenable to modern high‐performance computing platforms. However, the power consumption associated with distributed memory systems and graphical processing units does not align with modern energy policies. The porting of such applications to power‐efficient hardware platforms, such as field‐programmable gate arrays, requires a significant effort on the part of the software developer. The work detailed here enumerates the benefits of transitioning to energy‐efficient platforms.
Bibliographie:Funding information
H2020 European Research Council, Grant/Award Number: 671653; Royal Society, Grant/Award Numbers: RG140728, UF160398, UF110161; EU Horizon 2020, Grant/Award Number: 671653
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ISSN:0020-7608
1097-461X
DOI:10.1002/qua.25853