Efficient Implementation of a Threshold Modified Min-Sum Algorithm for LDPC Decoders
In this brief, we present a hardware efficient implementation of a threshold modified min-sum algorithm (MSA) to improve the performance of a low density parity-check (LDPC) decoder. The proposed architecture introduces a novel lookup table based threshold attenuation technique, called threshold att...
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| Published in: | IEEE transactions on circuits and systems. II, Express briefs Vol. 67; no. 9; pp. 1599 - 1603 |
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| Main Authors: | , , |
| Format: | Journal Article |
| Language: | English |
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New York
IEEE
01.09.2020
The Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
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| ISSN: | 1549-7747, 1558-3791 |
| Online Access: | Get full text |
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| Abstract | In this brief, we present a hardware efficient implementation of a threshold modified min-sum algorithm (MSA) to improve the performance of a low density parity-check (LDPC) decoder. The proposed architecture introduces a novel lookup table based threshold attenuation technique, called threshold attenuated MSA (TAMSA). The proposed TAMSA implementation is shown to improve bit error rate (BER) performance compared to the conventional AMSA and MSA. Furthermore, a layered version of the TAMSA implementation is investigated to reduce hardware cost. Utilizing circuit optimization techniques, including a parallel computing structure, the proposed layered TAMSA field-programmable gate array (FPGA) implementation results show that the modified architecture requires no extra circuit power or circuit area compared to conventional AMSA, and only 0.07% extra leaf cells compared to conventional MSA. |
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| AbstractList | In this brief, we present a hardware efficient implementation of a threshold modified min-sum algorithm (MSA) to improve the performance of a low density parity-check (LDPC) decoder. The proposed architecture introduces a novel lookup table based threshold attenuation technique, called threshold attenuated MSA (TAMSA). The proposed TAMSA implementation is shown to improve bit error rate (BER) performance compared to the conventional AMSA and MSA. Furthermore, a layered version of the TAMSA implementation is investigated to reduce hardware cost. Utilizing circuit optimization techniques, including a parallel computing structure, the proposed layered TAMSA field-programmable gate array (FPGA) implementation results show that the modified architecture requires no extra circuit power or circuit area compared to conventional AMSA, and only 0.07% extra leaf cells compared to conventional MSA. |
| Author | Liu, Yanfang Tang, Wei Mitchell, David G. M. |
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| SubjectTerms | Algorithms Architecture Attenuation Bit error rate Circuits Decoders Decoding Field programmable gate arrays FPGA Hardware LDPC codes LDPC decoder Lookup tables min-sum algorithm Optimization Optimization techniques Parity check codes Performance enhancement Signal to noise ratio Table lookup |
| Title | Efficient Implementation of a Threshold Modified Min-Sum Algorithm for LDPC Decoders |
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