Concatenated BCH and LDPC Coding Scheme With Iterative Decoding Algorithm for Flash Memory
As adopting a very powerful error-correcting code gradually becomes a strategic demand for the endurance of nowadays flash memory, LDPC codes are recently proposed due to their outstanding error correcting capability. However, the error floor phenomenon of LDPC codes might not meet the extreme low e...
Saved in:
| Published in: | IEEE communications letters Vol. 19; no. 3; pp. 327 - 330 |
|---|---|
| Main Author: | |
| Format: | Journal Article |
| Language: | English |
| Published: |
New York
IEEE
01.03.2015
The Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Subjects: | |
| ISSN: | 1089-7798, 1558-2558 |
| Online Access: | Get full text |
| Tags: |
Add Tag
No Tags, Be the first to tag this record!
|
| Abstract | As adopting a very powerful error-correcting code gradually becomes a strategic demand for the endurance of nowadays flash memory, LDPC codes are recently proposed due to their outstanding error correcting capability. However, the error floor phenomenon of LDPC codes might not meet the extreme low error rate requirement of flash memory applications. Thus, concatenation of BCH and LDPC codes that strikes a balance between superb error correcting capability and low error floor becomes an alternative system structure. In this work, a modification of such concatenated coding system in Chen et al. [IEEE Commun. Lett., vol. 17, no. 5, pp. 980-983, May 2013] is proposed. Compared with the previous concatenated coding system via simulations, our design improves the error correcting capability in the waterfall region while keeps low error floor. |
|---|---|
| AbstractList | As adopting a very powerful error-correcting code gradually becomes a strategic demand for the endurance of nowadays flash memory, LDPC codes are recently proposed due to their outstanding error correcting capability. However, the error floor phenomenon of LDPC codes might not meet the extreme low error rate requirement of flash memory applications. Thus, concatenation of BCH and LDPC codes that strikes a balance between superb error correcting capability and low error floor becomes an alternative system structure. In this work, a modification of such concatenated coding system in Chen et al. [IEEE Commun. Lett., vol. 17, no. 5, pp. 980-983, May 2013] is proposed. Compared with the previous concatenated coding system via simulations, our design improves the error correcting capability in the waterfall region while keeps low error floor. |
| Author | Shin-Lin Shieh |
| Author_xml | – sequence: 1 givenname: Shin-Lin surname: Shieh fullname: Shieh, Shin-Lin |
| BookMark | eNp9kF1LwzAUhoNMcE7_gN4EvO5M0qYfl7NzbtAxQUXwpqTpydbRJjPthP17Mzu88MKLfMA5zzm8zyUaaKMBoRtKxpSS5D5LV8vlmBHKx8xPKAvJGRpSzmOPuWvg_iROvChK4gt02bZbQkjMOB2ij9RoKTrQ7pT4IZ1joUucTZ9TnJqy0mv8IjfQAH6vug1edGBFV30BnoLsy5N6bayrNVgZi2e1aDd4CY2xhyt0rkTdwvXpHaG32eNrOvey1dMinWSeZAnvvDIgfqiYirkkSalCyuKChYKFhYwUFTQqCk4SVqooYMAKl04EhIQKBJNKQuGP0F0_d2fN5x7aLt-avdVuZU7D0PdJwDlxXXHfJa1pWwsql1XnshjdWVHVOSX50WT-YzI_msxPJh3K_qA7WzXCHv6HbnuoAoBfIHLeg9j3vwHPBIAp |
| CODEN | ICLEF6 |
| CitedBy_id | crossref_primary_10_1109_TCSII_2019_2960484 crossref_primary_10_1109_ACCESS_2018_2880997 crossref_primary_10_1109_TCSI_2019_2915574 crossref_primary_10_1016_j_aeue_2017_10_033 crossref_primary_10_1109_TVT_2021_3102178 crossref_primary_10_1007_s12652_021_03254_1 |
| Cites_doi | 10.1109/TIT.2004.831841 10.1109/ITA.2014.6804221 10.1109/LCOMM.2013.031913.130142 10.1109/LCOMM.2003.814716 10.1109/26.494301 10.1109/GLOCOMW.2010.5700263 |
| ContentType | Journal Article |
| Copyright | Copyright The Institute of Electrical and Electronics Engineers, Inc. (IEEE) 2015 |
| Copyright_xml | – notice: Copyright The Institute of Electrical and Electronics Engineers, Inc. (IEEE) 2015 |
| DBID | 97E RIA RIE AAYXX CITATION 7SP 8FD L7M |
| DOI | 10.1109/LCOMM.2015.2391260 |
| DatabaseName | IEEE All-Society Periodicals Package (ASPP) 2005–Present IEEE All-Society Periodicals Package (ASPP) 1998–Present IEEE/IET Electronic Library CrossRef Electronics & Communications Abstracts Technology Research Database Advanced Technologies Database with Aerospace |
| DatabaseTitle | CrossRef Technology Research Database Advanced Technologies Database with Aerospace Electronics & Communications Abstracts |
| DatabaseTitleList | Technology Research Database |
| Database_xml | – sequence: 1 dbid: RIE name: IEEE Electronic Library (IEL) url: https://ieeexplore.ieee.org/ sourceTypes: Publisher |
| DeliveryMethod | fulltext_linktorsrc |
| Discipline | Engineering |
| EISSN | 1558-2558 |
| EndPage | 330 |
| ExternalDocumentID | 3623504061 10_1109_LCOMM_2015_2391260 7008483 |
| Genre | orig-research |
| GroupedDBID | -~X 0R~ 29I 4.4 5GY 5VS 6IK 97E AAJGR AARMG AASAJ AAWTH ABAZT ABQJQ ABVLG ACGFO ACIWK AENEX AETIX AGQYO AGSQL AHBIQ AI. AIBXA AKJIK AKQYR ALLEH ALMA_UNASSIGNED_HOLDINGS ATWAV AZLTO BEFXN BFFAM BGNUA BKEBE BPEOZ CS3 DU5 EBS EJD HZ~ H~9 IES IFIPE IFJZH IPLJI JAVBF LAI M43 O9- OCL P2P RIA RIE RNS TN5 VH1 AAYXX CITATION 7SP 8FD L7M RIG |
| ID | FETCH-LOGICAL-c295t-d4036f2f85c09df6128b26a26bc7f1a17bb5092df742e2b391a4006fea2cfceb3 |
| IEDL.DBID | RIE |
| ISICitedReferencesCount | 8 |
| ISICitedReferencesURI | http://www.webofscience.com/api/gateway?GWVersion=2&SrcApp=Summon&SrcAuth=ProQuest&DestLinkType=CitingArticles&DestApp=WOS_CPL&KeyUT=000351407800005&url=https%3A%2F%2Fcvtisr.summon.serialssolutions.com%2F%23%21%2Fsearch%3Fho%3Df%26include.ft.matches%3Dt%26l%3Dnull%26q%3D |
| ISSN | 1089-7798 |
| IngestDate | Mon Jun 30 10:25:33 EDT 2025 Sat Nov 29 06:26:33 EST 2025 Tue Nov 18 21:02:36 EST 2025 Wed Aug 27 02:48:16 EDT 2025 |
| IsPeerReviewed | true |
| IsScholarly | true |
| Issue | 3 |
| Keywords | flash memory error floor concatenated code BCH code Low-density parity-check code |
| Language | English |
| License | https://ieeexplore.ieee.org/Xplorehelp/downloads/license-information/IEEE.html |
| LinkModel | DirectLink |
| MergedId | FETCHMERGED-LOGICAL-c295t-d4036f2f85c09df6128b26a26bc7f1a17bb5092df742e2b391a4006fea2cfceb3 |
| Notes | ObjectType-Article-1 SourceType-Scholarly Journals-1 ObjectType-Feature-2 content type line 14 |
| PQID | 1663304550 |
| PQPubID | 85419 |
| PageCount | 4 |
| ParticipantIDs | crossref_primary_10_1109_LCOMM_2015_2391260 crossref_citationtrail_10_1109_LCOMM_2015_2391260 proquest_journals_1663304550 ieee_primary_7008483 |
| PublicationCentury | 2000 |
| PublicationDate | 2015-March 2015-3-00 20150301 |
| PublicationDateYYYYMMDD | 2015-03-01 |
| PublicationDate_xml | – month: 03 year: 2015 text: 2015-March |
| PublicationDecade | 2010 |
| PublicationPlace | New York |
| PublicationPlace_xml | – name: New York |
| PublicationTitle | IEEE communications letters |
| PublicationTitleAbbrev | COML |
| PublicationYear | 2015 |
| Publisher | IEEE The Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Publisher_xml | – name: IEEE – name: The Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| References | ref8 ref7 richardson (ref5) 0 ref9 lin (ref4) 2004 ref3 ref6 ref1 cai (ref2) 0 |
| References_xml | – ident: ref3 doi: 10.1109/TIT.2004.831841 – start-page: 521 year: 0 ident: ref2 article-title: Error patterns in MLC NAND flash memory: Measurement, characterization, analysis publication-title: Proc Des Autom Test Eur Conf Exhib – start-page: 1426 year: 0 ident: ref5 article-title: Error floors of LDPC codes publication-title: Proc Allerton Conf Commun Control Comput – ident: ref9 doi: 10.1109/ITA.2014.6804221 – ident: ref6 doi: 10.1109/LCOMM.2013.031913.130142 – year: 2004 ident: ref4 publication-title: Error Control Coding – ident: ref8 doi: 10.1109/LCOMM.2003.814716 – ident: ref7 doi: 10.1109/26.494301 – ident: ref1 doi: 10.1109/GLOCOMW.2010.5700263 |
| SSID | ssj0008251 |
| Score | 2.1667042 |
| Snippet | As adopting a very powerful error-correcting code gradually becomes a strategic demand for the endurance of nowadays flash memory, LDPC codes are recently... |
| SourceID | proquest crossref ieee |
| SourceType | Aggregation Database Enrichment Source Index Database Publisher |
| StartPage | 327 |
| SubjectTerms | Ash Bit error rate Decoding Encoding Iterative decoding Reliability |
| Title | Concatenated BCH and LDPC Coding Scheme With Iterative Decoding Algorithm for Flash Memory |
| URI | https://ieeexplore.ieee.org/document/7008483 https://www.proquest.com/docview/1663304550 |
| Volume | 19 |
| WOSCitedRecordID | wos000351407800005&url=https%3A%2F%2Fcvtisr.summon.serialssolutions.com%2F%23%21%2Fsearch%3Fho%3Df%26include.ft.matches%3Dt%26l%3Dnull%26q%3D |
| hasFullText | 1 |
| inHoldings | 1 |
| isFullTextHit | |
| isPrint | |
| journalDatabaseRights | – providerCode: PRVIEE databaseName: IEEE Electronic Library (IEL) customDbUrl: eissn: 1558-2558 dateEnd: 99991231 omitProxy: false ssIdentifier: ssj0008251 issn: 1089-7798 databaseCode: RIE dateStart: 19970101 isFulltext: true titleUrlDefault: https://ieeexplore.ieee.org/ providerName: IEEE |
| link | http://cvtisr.summon.serialssolutions.com/2.0.0/link/0/eLvHCXMwlV1LS8NAEB5UPOjBt1hf7MGbRrPb5rFHjRaFVgUVxUvYpxVsIm0V_PfObtIqKIKHQGB3Q5gvO_NNdh4Ae1KGqbShCpo6dSk5LdSDrbAZCB4pGjONFt0nCneSy8v04YFfT8HBJBfGGOODz8yhu_Vn-bpUb-5X2VHiq783p2E6SeIqV2uidV0KZhVMz5Ex8nScIBPyo0521e26KK7okDU5Zb4c5ZcR8l1Vfqhib1_ai_97syVYqHkkOa6AX4YpU6zA_LfqgqvwmJWu4qsp8NLkJDsnotCkc3qdkax0JovcIGJ9Q-6fRz1y4csro-4jp-iR-uHjl6dygGN9gsyWtJFn90jXReZ-rMFd--w2Ow_qVgqBYjwaBRrlH1tm00iFXFukNalksWCxVImlgiZSInNg2qKnbJhEKQnc3LE1gimr0OFeh5miLMwGEKokE4wJzqhuxZqKxIoolIrZxIgo1g2gY9nmqq4z7tpdvOTe3wh57vHIHR55jUcD9idrXqsqG3_OXnUITGbWwm_A9hjCvN6Iw5wio3KHwVG4-fuqLZhzz67CyrZhZjR4Mzswq95Hz8PBrv_GPgEHl8z_ |
| linkProvider | IEEE |
| linkToHtml | http://cvtisr.summon.serialssolutions.com/2.0.0/link/0/eLvHCXMwlV1LT9tAEB6lUKnlUFpC1dDQ7oEbdfBu4sceqWmUqE6IRBARF2ufBQlsFEKl_ntmN06o1AqJgyVLuytb83nn4Z35BuBAyjCVNlRBV6euJKeHerAXdgPBI0VjptGi-0LhPBmP09mMTxrwbV0LY4zxyWem4279Wb6u1IP7VXaUePb37ivYdJ2z6mqttd51RZjLdHqOPiNPVyUyIT_Ks9PRyOVxRR3W5ZR5QsonM-T7qvyjjL2F6W-_7N3ew7vakyTHS-g_QMOUO7D1F79gEy6zynG-mhIvTb5nAyJKTfKTSUayyhktcoaY3Rpycb24IkNPsIzaj5xgTOqHj29-VXMcuyXo25I-etpXZORyc__swnn_xzQbBHUzhUAxHi0CjQjEltk0UiHXFh2bVLJYsFiqxFJBEynRd2DaYqxsmEQpCdzesTWCKasw5P4IG2VVmk9AqJJMMCY4o7oXayoSK6JQKmYTI6JYt4CuZFuommncNby4KXzEEfLC41E4PIoajxYcrtfcLXk2np3ddAisZ9bCb0F7BWFRb8X7gqJP5Y6Do3Dv_6u-wpvBdJQX-XD88zO8dc9ZJpm1YWMxfzD78Fr9Xlzfz7_47-0R4N7QSA |
| openUrl | ctx_ver=Z39.88-2004&ctx_enc=info%3Aofi%2Fenc%3AUTF-8&rfr_id=info%3Asid%2Fsummon.serialssolutions.com&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Ajournal&rft.genre=article&rft.atitle=Concatenated+BCH+and+LDPC+Coding+Scheme+With+Iterative+Decoding+Algorithm+for+Flash+Memory&rft.jtitle=IEEE+communications+letters&rft.au=Shieh%2C+Shin-Lin&rft.date=2015-03-01&rft.pub=The+Institute+of+Electrical+and+Electronics+Engineers%2C+Inc.+%28IEEE%29&rft.issn=1089-7798&rft.eissn=1558-2558&rft.volume=19&rft.issue=3&rft.spage=327&rft_id=info:doi/10.1109%2FLCOMM.2015.2391260&rft.externalDBID=NO_FULL_TEXT&rft.externalDocID=3623504061 |
| thumbnail_l | http://covers-cdn.summon.serialssolutions.com/index.aspx?isbn=/lc.gif&issn=1089-7798&client=summon |
| thumbnail_m | http://covers-cdn.summon.serialssolutions.com/index.aspx?isbn=/mc.gif&issn=1089-7798&client=summon |
| thumbnail_s | http://covers-cdn.summon.serialssolutions.com/index.aspx?isbn=/sc.gif&issn=1089-7798&client=summon |