Dual-Channel Multiplier for Piecewise-Polynomial Function Evaluation for Low-Power 3-D Graphics
A dual-channel multiplier (DCM) for energy efficient second-order piecewise-polynomial function evaluation for 3-D graphics applications is presented in this paper. The performance of the evaluation process is highly dependent on the design of the multiplication and squaring structure. A novel hardw...
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| Published in: | IEEE transactions on very large scale integration (VLSI) systems Vol. 27; no. 4; pp. 790 - 798 |
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| Main Authors: | , , , |
| Format: | Journal Article |
| Language: | English |
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New York
IEEE
01.04.2019
The Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
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| ISSN: | 1063-8210, 1557-9999 |
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| Abstract | A dual-channel multiplier (DCM) for energy efficient second-order piecewise-polynomial function evaluation for 3-D graphics applications is presented in this paper. The performance of the evaluation process is highly dependent on the design of the multiplication and squaring structure. A novel hardware implementation for polynomial evaluation is presented. The proposed approach compensates the complex multipliers by using DCM which reduces the hardware complexity. The DCM scheme performs complex functions with power-efficient and area-efficient approach. The multiplier reduces the hardware computational effort in the piecewise polynomial approximation with uniform or nonuniform segmentation. For large operand input size, a multiplier adder converter and a dedicated radix-4 squaring unit are also proposed. These units achieve the least power consumption compared to previous approaches with large input word size. Comparison with general purpose multiplication has shown reduction in power, and delay by up to 36%, and 50%, respectively. The proposed technique exhibits up to 93% saving in power consumption compared to the current traditional schemes. |
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| AbstractList | A dual-channel multiplier (DCM) for energy efficient second-order piecewise-polynomial function evaluation for 3-D graphics applications is presented in this paper. The performance of the evaluation process is highly dependent on the design of the multiplication and squaring structure. A novel hardware implementation for polynomial evaluation is presented. The proposed approach compensates the complex multipliers by using DCM which reduces the hardware complexity. The DCM scheme performs complex functions with power-efficient and area-efficient approach. The multiplier reduces the hardware computational effort in the piecewise polynomial approximation with uniform or nonuniform segmentation. For large operand input size, a multiplier adder converter and a dedicated radix-4 squaring unit are also proposed. These units achieve the least power consumption compared to previous approaches with large input word size. Comparison with general purpose multiplication has shown reduction in power, and delay by up to 36%, and 50%, respectively. The proposed technique exhibits up to 93% saving in power consumption compared to the current traditional schemes. |
| Author | Zekry, Abdelhalim Zaki, Amal Ellaithy, Dina M. El-Moursy, Magdy A. |
| Author_xml | – sequence: 1 givenname: Dina M. surname: Ellaithy fullname: Ellaithy, Dina M. email: dina_elessy@eri.sci.eg organization: Microelectronics Department, Electronics Research Institute, Cairo, Egypt – sequence: 2 givenname: Magdy A. orcidid: 0000-0002-9890-4651 surname: El-Moursy fullname: El-Moursy, Magdy A. email: magdy_el-moursy@mentor.com organization: Microelectronics Department, Electronics Research Institute, Cairo, Egypt – sequence: 3 givenname: Amal surname: Zaki fullname: Zaki, Amal organization: Microelectronics Department, Electronics Research Institute, Cairo, Egypt – sequence: 4 givenname: Abdelhalim surname: Zekry fullname: Zekry, Abdelhalim email: aaazekry@hotmail.com organization: Electronics and Communications Department, Ain Shams University, Cairo, Egypt |
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| SubjectTerms | 3-D graphics Approximation algorithms Channel multipliers Clocks Complexity Computer architecture Converters Dual channel multiplier (DCM) Energy conservation graphical processing unit (GPU) Graphics processing units Hardware low power Multiplication multiplier adder converter (MAC) piecewuise-polynomial evaluation Polynomials Power consumption Power demand radix-4 squaring unit Segmentation Very large scale integration |
| Title | Dual-Channel Multiplier for Piecewise-Polynomial Function Evaluation for Low-Power 3-D Graphics |
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