An Efficient and High-Speed Overlap-Free Karatsuba-Based Finite-Field Multiplier for FGPA Implementation

Cryptography systems have become inseparable parts of almost every communication device. Among cryptography algorithms, public-key cryptography, and in particular elliptic curve cryptography (ECC), has become the most dominant protocol at this time. In ECC systems, polynomial multiplication is consi...

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Vydáno v:IEEE transactions on very large scale integration (VLSI) systems Ročník 29; číslo 4; s. 667 - 676
Hlavní autoři: Heidarpur, Moslem, Mirhassani, Mitra
Médium: Journal Article
Jazyk:angličtina
Vydáno: New York IEEE 01.04.2021
The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Témata:
Algorithms
Binary polynomial multiplier
Complexity theory
Cryptography
Curves
Delays
Elliptic curve cryptography
Field programmable gate arrays
field-programmable gate array (FPGA) implementation
finite-field multiplier
Galois field
Hardware
hardware cryptography
Logic gates
Multiplication
overlap-free Karatsuba
Polynomials
ISSN:1063-8210, 1557-9999
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Shrnutí:Cryptography systems have become inseparable parts of almost every communication device. Among cryptography algorithms, public-key cryptography, and in particular elliptic curve cryptography (ECC), has become the most dominant protocol at this time. In ECC systems, polynomial multiplication is considered to be the most slow and area consuming operation. This article proposes a novel hardware architecture for efficient field-programmable gate array (FPGA) implementation of Finite-field multipliers for ECC. Proposed hardware was implemented on different FPGA devices for various operand sizes, and performance parameters were determined. Comparing to state-of-the-art works, the proposed method resulted in a lower combinational delay and area-delay product indicating the efficiency of design.
Bibliografie:ObjectType-Article-1
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ISSN:1063-8210
1557-9999
DOI:10.1109/TVLSI.2021.3058509