Digit-Level Serial-In Parallel-Out Multiplier Using Redundant Representation for a Class of Finite Fields
Two digit-level finite field multipliers in F 2 m using redundant representation are presented. Embedding F 2 m in cyclotomic field F 2 (n) causes a certain amount of redundancy and consequently performing field multiplication using redundant representation would require more hardware resources. Bas...
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| Vydáno v: | IEEE transactions on very large scale integration (VLSI) systems Ročník 25; číslo 5; s. 1632 - 1643 |
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| Médium: | Journal Article |
| Jazyk: | angličtina |
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New York
IEEE
01.05.2017
The Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
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| ISSN: | 1063-8210, 1557-9999 |
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| Abstract | Two digit-level finite field multipliers in F 2 m using redundant representation are presented. Embedding F 2 m in cyclotomic field F 2 (n) causes a certain amount of redundancy and consequently performing field multiplication using redundant representation would require more hardware resources. Based on a specific feature of redundant representation in a class of finite fields, two new multiplication algorithms along with their pertaining architectures are proposed to alleviate this problem. Considering area-delay product as a measure of evaluation, it has been shown that both the proposed architectures considerably outperform existing digit-level multipliers using the same basis. It is also shown that for a subset of the fields, the proposed multipliers are of higher performance in terms of area-delay complexities among several recently proposed optimal normal basis multipliers. The main characteristics of the postplace&route application specific integrated circuit implementation of the proposed multipliers for three practical digit sizes are also reported. |
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| AbstractList | Two digit-level finite field multipliers in [Formula Omitted] using redundant representation are presented. Embedding [Formula Omitted] in cyclotomic field [Formula Omitted] causes a certain amount of redundancy and consequently performing field multiplication using redundant representation would require more hardware resources. Based on a specific feature of redundant representation in a class of finite fields, two new multiplication algorithms along with their pertaining architectures are proposed to alleviate this problem. Considering area-delay product as a measure of evaluation, it has been shown that both the proposed architectures considerably outperform existing digit-level multipliers using the same basis. It is also shown that for a subset of the fields, the proposed multipliers are of higher performance in terms of area-delay complexities among several recently proposed optimal normal basis multipliers. The main characteristics of the postplace&route application specific integrated circuit implementation of the proposed multipliers for three practical digit sizes are also reported. Two digit-level finite field multipliers in F 2 m using redundant representation are presented. Embedding F 2 m in cyclotomic field F 2 (n) causes a certain amount of redundancy and consequently performing field multiplication using redundant representation would require more hardware resources. Based on a specific feature of redundant representation in a class of finite fields, two new multiplication algorithms along with their pertaining architectures are proposed to alleviate this problem. Considering area-delay product as a measure of evaluation, it has been shown that both the proposed architectures considerably outperform existing digit-level multipliers using the same basis. It is also shown that for a subset of the fields, the proposed multipliers are of higher performance in terms of area-delay complexities among several recently proposed optimal normal basis multipliers. The main characteristics of the postplace&route application specific integrated circuit implementation of the proposed multipliers for three practical digit sizes are also reported. |
| Author | Namin, Parham Hosseinzadeh Muscedere, Roberto Ahmadi, Majid |
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| References | ref13 ref12 ref15 ref14 (ref25) 2006 ref11 ref10 kerry (ref19) 2013 ref2 ref1 ref17 ref18 omura (ref7) 1986 namin (ref23) 2006 lidl (ref16) 1997 ref24 ref20 ref22 ref21 memezes (ref3) 1996 mastrovito (ref6) 1991 ref8 ref9 ref4 ref5 |
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| Snippet | Two digit-level finite field multipliers in F 2 m using redundant representation are presented. Embedding F 2 m in cyclotomic field F 2 (n) causes a certain... Two digit-level finite field multipliers in [Formula Omitted] using redundant representation are presented. Embedding [Formula Omitted] in cyclotomic field... |
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| SubjectTerms | Complexity theory Computer architecture Delay Digit-level architecture Elliptic curve cryptography finite field arithmetic Hardware Multiplication multiplication algorithm Multipliers Niobium Redundancy redundant representation |
| Title | Digit-Level Serial-In Parallel-Out Multiplier Using Redundant Representation for a Class of Finite Fields |
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