High-Throughput and Energy-Efficient VLSI Architecture for Ordered Reliability Bits GRAND

Ultrareliable low-latency communication (URLLC), a major 5G new-radio (NR) use case, is the key enabler for applications with strict reliability and latency requirements. These applications necessitate the use of short-length and high-rate channel codes. Guessing random additive noise decoding (GRAN...

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Vydáno v:IEEE transactions on very large scale integration (VLSI) systems Ročník 30; číslo 6; s. 681 - 693
Hlavní autoři: Abbas, Syed Mohsin, Tonnellier, Thibaud, Ercan, Furkan, Jalaleddine, Marwan, Gross, Warren J.
Médium: Journal Article
Jazyk:angličtina
Vydáno: New York IEEE 01.06.2022
The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Témata:
Area efficiency
Codes
Decoding
Energy efficiency
error-correcting code (ECC)
guessing random additive noise decoding (GRAND)
Hardware
Integrated circuits
Maximum likelihood decoding
maximum likelihood decoding (MLD)
Network latency
ordered reliability bits GRAND (ORBGRAND)
Polar codes
Reliability
Throughput
Very large scale integration
VLSI architecture
ISSN:1063-8210, 1557-9999
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Shrnutí:Ultrareliable low-latency communication (URLLC), a major 5G new-radio (NR) use case, is the key enabler for applications with strict reliability and latency requirements. These applications necessitate the use of short-length and high-rate channel codes. Guessing random additive noise decoding (GRAND) is a recently proposed maximum likelihood (ML) decoding technique for these short-length and high-rate codes. Rather than decoding the received vector, GRAND tries to infer the noise that corrupted the transmitted codeword during transmission through the communication channel. As a result, GRAND can decode any code, structured or unstructured. GRAND has hard-input as well as soft-input variants. Among these variants, ordered reliability bits GRAND (ORBGRAND) is a soft-input variant that outperforms hard-input GRAND and is suitable for parallel hardware implementation. This work reports the first hardware architecture for ORBGRAND, which achieves an average throughput of up to 42.5 Gb/s for a code length of 128 at a target frame error rate (FER) of 10 −7 . Furthermore, the proposed hardware can be used to decode any code as long as the length and rate constraints are met. In comparison to the GRAND with ABandonment (GRANDAB), a hard-input variant of GRAND, the proposed architecture enhances decoding performance by at least 2 dB. When compared to the state-of-the-art fast dynamic successive cancellation flip decoder (Fast-DSCF) using a 5G polar code (PC) (128, 105), the proposed ORBGRAND VLSI implementation has <inline-formula> <tex-math notation="LaTeX">49\times </tex-math></inline-formula> higher average throughput, <inline-formula> <tex-math notation="LaTeX">32\times </tex-math></inline-formula> times more energy efficiency, and <inline-formula> <tex-math notation="LaTeX">5\times </tex-math></inline-formula> more area efficiency while maintaining similar decoding performance.
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ISSN:1063-8210
1557-9999
DOI:10.1109/TVLSI.2022.3153605