A Distributed and Parallel Accelerator Design for 3-D Acoustic Imaging on FPGA-Based Systems

3-D imaging sonar is crucial in the exploration of marine resources, and the development of portable device with high-imaging quality and high-real-time performance is the general trend. However, traditional framework methods are limited by the huge amount of computation brought by high-quality imag...

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Published in:IEEE transactions on computer-aided design of integrated circuits and systems Vol. 43; no. 5; pp. 1401 - 1414
Main Authors: Zhao, Dongdong, Mao, Weibo, Chen, Peng, Hu, Yingtian, Liang, Haoran, Dang, Yuanjie, Liang, Ronghua, Guo, Xinxin
Format: Journal Article
Language:English
Published: New York IEEE 01.05.2024
The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subjects:
3-D acoustic imaging
Acoustic beams
Acoustic imaging
algorithm-hardware co-designed
Algorithms
Array signal processing
Beamforming
Computer architecture
distributed and parallel architecture
Field programmable gate arrays
fieldprogrammable gate array (FPGA)-based accelerator
Imaging
Marine resources
Mathematical analysis
Portable equipment
Real time
Sonar
Three dimensional imaging
Transducers
Ultra wideband technology
Ultrawideband
ISSN:0278-0070, 1937-4151
Online Access:Get full text
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Summary:3-D imaging sonar is crucial in the exploration of marine resources, and the development of portable device with high-imaging quality and high-real-time performance is the general trend. However, traditional framework methods are limited by the huge amount of computation brought by high-quality imaging, making it difficult to implement in engineering. To address this issue, we develop 3-D real-time sonar system in an algorithm-hardware co-designed way. An ultrawideband distributed and parallel subarray beamforming algorithm (UWB-DPS) is proposed for 3-D acoustic imaging. This is a multistage array time-frequency beamforming method under a distributed parallel computing architecture. Based on this, we propose field-programmable gate array (FPGA)-based accelerator. It divides a large sonar receiving planar array into multiple parallel subarrays, and complete the beamforming in two stages, which can reduce the calculation load and speeds up 3-D imaging. For engineering implementation, we optimized the sparseness of the planar transducer array, with a sparse rate as high as 97.7%. The experimental results show that the calculation amount of the proposed UWB-DPS algorithm is reduced to 1/5.7 of the traditional framework algorithm, the imaging performance is effectively improved, and the FPGA-based accelerator outperforms the CPU software implementation by 935<inline-formula> <tex-math notation="LaTeX">\times </tex-math></inline-formula>.
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ISSN:0278-0070
1937-4151
DOI:10.1109/TCAD.2023.3340128