3-D In-Sensor Computing for Real-Time DVS Data Compression: 65-nm Hardware-Algorithm Co-Design

Traditional IO links are insufficient to transport high volume of image sensor data, under stringent power and latency constraints. To address this, we demonstrate a low latency, low power in-sensor computing architecture to compress the data from a 3D-stacked dynamic vision sensor (DVS). In this de...

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Veröffentlicht in:IEEE solid-state circuits letters Jg. 7; S. 119 - 122
Hauptverfasser: Nair, Gopikrishnan R., Nalla, Pragnya S., Krishnan, Gokul, Anupreetham, Oh, Jonghyun, Hassan, Ahmed, Yeo, Injune, Kasichainula, Kishore, Seok, Mingoo, Seo, Jae-Sun, Cao, Yu
Format: Journal Article
Sprache:Englisch
Veröffentlicht: Piscataway IEEE 2024
The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
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ISSN:2573-9603, 2573-9603
Online-Zugang:Volltext
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