Online Reset for Signal Temporal Logic Monitoring

Online monitoring is a popular validation approach in which the temporal behavior of a system is checked to assess whether it satisfies a given specification expressed, e.g., in signal temporal logic (STL). This is done by employing a monitor that, at each time point, states the specification validi...

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Published in:IEEE transactions on computer-aided design of integrated circuits and systems Vol. 41; no. 11; pp. 4421 - 4432
Main Authors: Zhang, Zhenya, Arcaini, Paolo, Xie, Xuan
Format: Journal Article
Language:English
Published: New York IEEE 01.11.2022
The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
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ISSN:0278-0070, 1937-4151
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Abstract Online monitoring is a popular validation approach in which the temporal behavior of a system is checked to assess whether it satisfies a given specification expressed, e.g., in signal temporal logic (STL). This is done by employing a monitor that, at each time point, states the specification validity: satisfied, violated, or unknown. In some settings, monitoring should continue even after a violation episode is detected, to detect possible future violation episodes. However, for a monitor just relying on STL semantics, this is not possible, as, once the specification is violated by an input signal, any continuation of the signal still violates the specification. To tackle this problem, we here propose an optimal reset technique that, at runtime, detects the end of a violation episode and shifts the evaluation of the monitor to skip such an episode. In this way, the monitoring can continue to detect possible other future violation episodes. We propose a framework that integrates the reset technique with an existing monitoring approach. Experiments on two Simulink models show that the technique can effectively reset the monitor and report all the violation episodes, with a negligible overhead on the monitoring cost.
AbstractList Online monitoring is a popular validation approach in which the temporal behavior of a system is checked to assess whether it satisfies a given specification expressed, e.g., in signal temporal logic (STL). This is done by employing a monitor that, at each time point, states the specification validity: satisfied, violated, or unknown. In some settings, monitoring should continue even after a violation episode is detected, to detect possible future violation episodes. However, for a monitor just relying on STL semantics, this is not possible, as, once the specification is violated by an input signal, any continuation of the signal still violates the specification. To tackle this problem, we here propose an optimal reset technique that, at runtime, detects the end of a violation episode and shifts the evaluation of the monitor to skip such an episode. In this way, the monitoring can continue to detect possible other future violation episodes. We propose a framework that integrates the reset technique with an existing monitoring approach. Experiments on two Simulink models show that the technique can effectively reset the monitor and report all the violation episodes, with a negligible overhead on the monitoring cost.
Author Arcaini, Paolo
Zhang, Zhenya
Xie, Xuan
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SubjectTerms Gears
Hybrid systems
monitor reset
Monitoring
online monitoring
Optimized production technology
Robustness
Runtime
Semantics
signal diagnostics
Signal monitoring
signal temporal logic (STL)
Specifications
Syntactics
Temporal logic
Title Online Reset for Signal Temporal Logic Monitoring
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