Synthesizing Formal Network Specifications From Input-Output Examples

We propose, a tool that synthesizes network specifications in a declarative logic programming language from input-output examples. aims to accelerate the adoption of formal verification in networking practice, by reducing the effort and expertise required to specify network models or properties. aim...

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Veröffentlicht in:	IEEE/ACM transactions on networking Jg. 31; H. 3; S. 1 - 16
Hauptverfasser:	Chen, Haoxian, Wu, Chenyuan, Zhao, Andrew, Raghothaman, Mukund, Naik, Mayur, Loo, Boon Thau
Format:	Journal Article
Sprache:	Englisch
Veröffentlicht:	New York IEEE 01.06.2023 The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Schlagworte:	Benchmark testing Consensus protocol Logic programming Network protocol program synthesis Programming languages Robustness (mathematics) Routing protocols Runtime Search algorithms Security Semantics Solution space Specifications Synthesis Task analysis Verification
ISSN:	1063-6692, 1558-2566
Online-Zugang:	Volltext
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