The Implementation and Optimization of Neuromorphic Hardware for Supporting Spiking Neural Networks With MLP and CNN Topologies

Spiking neural network (SNN) has attracted extensive attention in large-scale image processing tasks. To obtain higher computing efficiency, the development of hardware architecture suitable for SNN computing has become a hot research topic. However, the existing hardware of spike neurons still has...

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Vydané v:	IEEE transactions on computer-aided design of integrated circuits and systems Ročník 42; číslo 2; s. 448 - 461
Hlavní autori:	Ye, Wujian, Chen, Yuehai, Liu, Yijun
Médium:	Journal Article
Jazyk:	English
Vydavateľské údaje:	New York IEEE 01.02.2023 The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Predmet:	Acceleration Accuracy Artificial neural networks Biological system modeling Complexity Computational modeling Datasets Energy consumption Field programmable gate arrays Field-programmable gate array (FPGA) platform genetic algorithm (GA) Genetic algorithms Hardware hardware acceleration system Image processing Integrated circuit modeling leaky integrated-and-fire (LIF) neuron optimization Mathematical models Multilayer perceptrons Network topologies Neural networks Neuromorphic computing Neuromorphics Neurons Optimization Pipelining (computers) Spiking spiking neural network (SNN) acceleration
ISSN:	0278-0070, 1937-4151
On-line prístup:	Získať plný text
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