Evolutionary Approach to Approximate Digital Circuits Design

In approximate computing, the requirement of perfect functional behavior can be relaxed because some applications are inherently error resilient. Approximate circuits, which fall into the approximate computing paradigm, are designed in such a way that they do not fully implement the logic behavior g...

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Vydané v:IEEE transactions on evolutionary computation Ročník 19; číslo 3; s. 432 - 444
Hlavní autori: Vasicek, Zdenek, Sekanina, Lukas
Médium: Journal Article
Jazyk:English
Vydavateľské údaje: New York IEEE 01.06.2015
The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Predmet:
Approximation methods
Circuit synthesis
Delays
Logic gates
Power demand
Sociology
Statistics
Cartesian genetic programming (CGP)
population seeding
digital circuits
Approximate computing
ISSN:1089-778X, 1941-0026
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Shrnutí:In approximate computing, the requirement of perfect functional behavior can be relaxed because some applications are inherently error resilient. Approximate circuits, which fall into the approximate computing paradigm, are designed in such a way that they do not fully implement the logic behavior given by the specification and, hence, their accuracy can be exchanged for lower area, delay or power consumption. In order to automate the design process, we propose to evolve approximate digital circuits that show a minimal error for a supplied amount of resources. The design process, which is based on Cartesian genetic programming (CGP), can be repeated many times in order to obtain various tradeoffs between the accuracy and area. A heuristic seeding mechanism is introduced to CGP, which allows for improving not only the quality of evolved circuits, but also reducing the time of evolution. The efficiency of the proposed method is evaluated for the gate as well as the functional level evolution. In particular, approximate multipliers and median circuits that show very good parameters in comparison with other available implementations were constructed by means of the proposed method.
Bibliografia:ObjectType-Article-1
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content type line 14
ISSN:1089-778X
1941-0026
DOI:10.1109/TEVC.2014.2336175