CIM-Spin: A Scalable CMOS Annealing Processor With Digital In-Memory Spin Operators and Register Spins for Combinatorial Optimization Problems

Recently, annealing processors based on the Ising model have received rising attention as efficient alternative hardware for solving combinatorial optimization problems. After mapping a problem to the hardware Ising model, we can observe the natural convergence behavior of the Ising model and find p...

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Veröffentlicht in:	IEEE journal of solid-state circuits Jg. 57; H. 7; S. 2263 - 2273
Hauptverfasser:	Su, Yuqi, Kim, Hyunjoon, Kim, Bongjin
Format:	Journal Article
Sprache:	Englisch
Veröffentlicht:	New York IEEE 01.07.2022 The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Schlagworte:	Annealing Annealing processor Combinatorial analysis combinatorial optimization problem (COP) Computational modeling Hardware in-memory computing Integrated circuit modeling Ising model max-cut problem Microprocessors Optimization Random access memory Semiconductor device modeling
ISSN:	0018-9200, 1558-173X
Online-Zugang:	Volltext
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