Optimizing Graph Algorithms in Asymmetric Multicore Processors

Asymmetric multicore processors (AMP) fall under a special subcategory of modern-day heterogeneous multicore architectures with different participating core types executing a common instruction set architecture. The innate asymmetry in the performance of different cores in AMPs poses interesting cha...

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Bibliographic Details
Published in:IEEE transactions on computer-aided design of integrated circuits and systems Vol. 37; no. 11; pp. 2673 - 2684
Main Authors: Krishna, Jyothi V.S., Nasre, Rupesh
Format: Journal Article
Language:English
Published: New York IEEE 01.11.2018
The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subjects:
Algorithms
Arrays
Asymmetric multicore processors (AMP)
Asymmetry
Configurations
Dynamic scheduling
Embedded systems
Graph algorithms
Graph representations
Graphical representations
Instruction sets
Microprocessors
Multicore processing
Optimal scheduling
Optimization
parallel graph algorithms
Prediction algorithms
Processors
scheduling
Workloads
ISSN:0278-0070, 1937-4151
Online Access:Get full text
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Summary:Asymmetric multicore processors (AMP) fall under a special subcategory of modern-day heterogeneous multicore architectures with different participating core types executing a common instruction set architecture. The innate asymmetry in the performance of different cores in AMPs poses interesting challenges. Irregular workloads, such as graph algorithms, intensify these challenges as the parallel workloads in these algorithms cannot be precisely characterized at compile time. In this paper, we propose a framework named scheduler for irregular AMPs, which optimizes the efficiency of the given AMP system for a given algorithm-graph pair by optimizing the graph representation and using a predictor to find the optimal configurations to run the algorithm-graph pair. The optimization is performed in two stages: 1) finding an optimal graph representation and 2) finding an optimal hardware configuration to run the input algorithm-graph pair. We have tested the efficiency of our system on five different graph algorithms over eight real-world and synthetic graphs. On an average, we see 42.82% improvement in energy delay product over the base case.
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ISSN:0278-0070
1937-4151
DOI:10.1109/TCAD.2018.2858366