Efficient Reconfiguration Algorithm With Flexible Rerouting Schemes for Constructing 3-D VLSI Subarrays

In this paper, we investigated the technique for improving the reliability of 3-D processor with faults by reconfiguring a 3-D fault-free subarray utilizing as many nonfaulty process elements (PEs) as possible. A novel flexible rerouting scheme is proposed, which makes the PEs can be rerouted or byp...

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Veröffentlicht in:IEEE transactions on computer-aided design of integrated circuits and systems Jg. 39; H. 1; S. 267 - 271
Hauptverfasser: Qian, Junyan, Ding, Hao, Xiao, Hanpeng, Zhou, Zhide, Zhao, Lingzhong, Zhai, Zhongyi
Format: Journal Article
Sprache:Englisch
Veröffentlicht: New York IEEE 01.01.2020
The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
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ISSN:0278-0070, 1937-4151
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Zusammenfassung:In this paper, we investigated the technique for improving the reliability of 3-D processor with faults by reconfiguring a 3-D fault-free subarray utilizing as many nonfaulty process elements (PEs) as possible. A novel flexible rerouting scheme is proposed, which makes the PEs can be rerouted or bypassed in three dimensions, hence increasing the number of neighbors of each element to construct a logical array. Under this scheme, an efficient heuristic algorithm is presented to construct a logical array. The experimental results show that the proposed algorithm under flexible rerouting scheme can produce logical arrays with higher harvest from the host arrays with faults for the random fault scenarios, the improvement is by up to 46.47% compared to the state-of-the-arts.
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content type line 14
ISSN:0278-0070
1937-4151
DOI:10.1109/TCAD.2019.2891984