Efficient Reconfiguration Algorithm With Flexible Rerouting Schemes for Constructing 3-D VLSI Subarrays

In this paper, we investigated the technique for improving the reliability of 3-D processor with faults by reconfiguring a 3-D fault-free subarray utilizing as many nonfaulty process elements (PEs) as possible. A novel flexible rerouting scheme is proposed, which makes the PEs can be rerouted or byp...

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Bibliographic Details
Published in:IEEE transactions on computer-aided design of integrated circuits and systems Vol. 39; no. 1; pp. 267 - 271
Main Authors: Qian, Junyan, Ding, Hao, Xiao, Hanpeng, Zhou, Zhide, Zhao, Lingzhong, Zhai, Zhongyi
Format: Journal Article
Language:English
Published: New York IEEE 01.01.2020
The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subjects:
3-D processor array
Algorithms
Arrays
Circuit faults
Fault tolerance
Fault tolerant systems
Ground penetrating radar
Heuristic methods
Integrated circuits
Logic arrays
Microprocessors
Reconfiguration
rerouting algorithm
Switches
Three-dimensional displays
ISSN:0278-0070, 1937-4151
Online Access:Get full text
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Summary:In this paper, we investigated the technique for improving the reliability of 3-D processor with faults by reconfiguring a 3-D fault-free subarray utilizing as many nonfaulty process elements (PEs) as possible. A novel flexible rerouting scheme is proposed, which makes the PEs can be rerouted or bypassed in three dimensions, hence increasing the number of neighbors of each element to construct a logical array. Under this scheme, an efficient heuristic algorithm is presented to construct a logical array. The experimental results show that the proposed algorithm under flexible rerouting scheme can produce logical arrays with higher harvest from the host arrays with faults for the random fault scenarios, the improvement is by up to 46.47% compared to the state-of-the-arts.
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ISSN:0278-0070
1937-4151
DOI:10.1109/TCAD.2019.2891984