A New Variable Forgetting Factor-Based Bias-Compensated RLS Algorithm for Identification of FIR Systems With Input Noise and Its Hardware Implementation

This paper proposes a new variable forgetting factor QRD-based recursive least squares algorithm with bias compensation (VFF-QRRLS-BC) for system identification under input noise. A new variable forgetting factor scheme is proposed to improve its convergence speed and steady-state mean squares error...

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Bibliographic Details
Published in:IEEE transactions on circuits and systems. I, Regular papers Vol. 67; no. 1; pp. 198 - 211
Main Authors: Tan, Hai Jun, Chan, Shing Chow, Lin, Jian Qiang, Sun, Xu
Format: Journal Article
Language:English
Published: New York IEEE 01.01.2020
The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subjects:
Additive noise
Algorithms
Bias
bias compensation
Compensation
Computer simulation
efficient hardware implementation
Estimation
Field programmable gate arrays
Finite impulse response filters
Finite impulse response model
Hardware
Impulse response
Least squares method
Linear arrays
Lookup tables
Noise
Noise measurement
Recursive methods
Self calibration
Steady state
System identification
variable forgetting factor
ISSN:1549-8328, 1558-0806
Online Access:Get full text
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Summary:This paper proposes a new variable forgetting factor QRD-based recursive least squares algorithm with bias compensation (VFF-QRRLS-BC) for system identification under input noise. A new variable forgetting factor scheme is proposed to improve its convergence speed and steady-state mean squares error. A new method for recursive estimation of the additive noise variance is also proposed for reliable bias compensation. The mean and mean-square asymptotic behaviors of the algorithm are analyzed and a self-calibration scheme is further proposed to improve the steady-state mean squares error (MSE) due to finite sample effect. Simulations show that the proposed VFF approach offers improved tracking and steady-state MSE performance over the conventional recursive least squares method and its fixed FF counterpart. A linear array architecture is proposed for the realization of this algorithm and several hardware efficient techniques are introduced to avoid the expensive cubic root and division operations required. The proposed algorithm is validated on Xilinx Zynq ® -7000 AP SoC ZC702 Field Programmable Gate Array (FPGA). For a 10-tap finite impulse response (FIR) system, the implementation requires only about 11.5k slice look-up table (LUT)s, 4.5k slice registers and 50 DSP48s and it can work up to about 0.58 MHz sample rate with a 200 MHz system clock. The hardware resources are considerably lower than traditional techniques using divider and cubic root realization. The linear array architecture also serves as an attractive alternative to the systolic array in medium to low rate applications due to its reduced hardware usages.
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ISSN:1549-8328
1558-0806
DOI:10.1109/TCSI.2019.2944221