A Logic Synthesis Methodology for Low-Power Ternary Logic Circuits

We propose a logic synthesis methodology with a novel low-power circuit structure for ternary logic. The proposed methodology synthesizes a ternary function as a ternary logic gate using carbon nanotube field-effect transistors (CNTFETs). The circuit structure uses the body effect to mitigate the ex...

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Vydané v:	IEEE transactions on circuits and systems. I, Regular papers Ročník 67; číslo 9; s. 3138 - 3151
Hlavní autori:	Kim, Sunmean, Lee, Sung-Yun, Park, Sunghye, Kim, Kyung Rok, Kang, Seokhyeong
Médium:	Journal Article
Jazyk:	English
Vydavateľské údaje:	New York IEEE 01.09.2020 The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Predmet:	body effect Carbon nanotubes Circuit design Circuits CNTFETs Complexity theory Energy efficiency Field effect transistors Gates (circuits) Integrated circuit interconnections Logic circuits Logic gates Logic synthesis logic synthesis methodology Methodology Multi-valued logic Multivalued logic Power consumption Semiconductor devices ternary logic circuits
ISSN:	1549-8328, 1558-0806
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