An Ultra-Low-Power Dual-Mode Automatic Sleep Staging Processor Using Neural-Network-Based Decision Tree

This paper presents an ultra-low-power dual-mode automatic sleep staging processor design using a neural-network (NN)-based decision tree classifier to enable real-time, longterm, and flexible sleep monitoring. The ultra-low-power feature is achieved by an algorithm-hardware co-design approach that...

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Vydané v:IEEE transactions on circuits and systems. I, Regular papers Ročník 66; číslo 9; s. 3504 - 3516
Hlavní autori: Chang, Shang-Yuan, Wu, Bing-Chen, Liou, Yi-Long, Zheng, Rui-Xuan, Lee, Pei-Lin, Chiueh, Tzi-Dar, Liu, Tsung-Te
Médium: Journal Article
Jazyk:English
Vydavateľské údaje: New York IEEE 01.09.2019
The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Predmet:
Accuracy
Algorithms
Automatic sleep staging
Circuits
classifier
CMOS
CMOS VLSI design
Co-design
Datasets
decision tree
Decision trees
Design optimization
digital signal processing (DSP)
Electroencephalography
Electromyography
Feature extraction
hardware implementation
low power
Microprocessors
Monitoring
Neural networks
neuron network
Power consumption
Signal processing algorithms
Sleep
ISSN:1549-8328, 1558-0806
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Shrnutí:This paper presents an ultra-low-power dual-mode automatic sleep staging processor design using a neural-network (NN)-based decision tree classifier to enable real-time, longterm, and flexible sleep monitoring. The ultra-low-power feature is achieved by an algorithm-hardware co-design approach that jointly considers optimization opportunities across the algorithm, architecture, and circuit levels to minimize power consumption; consequently, the first sub-10-μW NN-based automatic sleep staging processor is realized. The dual-mode NN models are trained by an open-source large-scale dataset. The default mode achieves 81.0% classification accuracy based on two signals of one electroencephalography (EEG) signal and one electromyography (EMG) signal, and the compact mode achieves 78.5% accuracy based on only one EEG signal. In addition, the proposed design was verified using the National Taiwan University Hospital (NTUH) dataset, for which 81.1% and 77.1% accuracy is achieved in the default and the compact modes, respectively. A prototype chip using a 180-nm CMOS process occupies a total area of 11.74 mm 2 and operates at 10 KHz while consuming 4.96 μW at 1.2 V.
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ISSN:1549-8328
1558-0806
DOI:10.1109/TCSI.2019.2927839