A 28-nm Compute SRAM With Bit-Serial Logic/Arithmetic Operations for Programmable In-Memory Vector Computing

This article proposes a general-purpose hybrid in-/near-memory compute SRAM (CRAM) that combines an 8T transposable bit cell with vector-based, bit-serial in-memory arithmetic to accommodate a wide range of bit-widths, from single to 32 or 64 bits, as well as a complete set of operation types, inclu...

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Veröffentlicht in:	IEEE journal of solid-state circuits Jg. 55; H. 1; S. 76 - 86
Hauptverfasser:	Wang, Jingcheng, Wang, Xiaowei, Eckert, Charles, Subramaniyan, Arun, Das, Reetuparna, Blaauw, David, Sylvester, Dennis
Format:	Journal Article
Sprache:	Englisch
Veröffentlicht:	New York IEEE 01.01.2020 The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Schlagworte:	8T transposable bit cell Algorithms Arithmetic Bandwidth bit-serial arithmetic CMOS Computer architecture flexible bit-width Floating point arithmetic in-memory computing (IMC) Internet of Things memory Microprocessors Multiplication near-memory computing Neural networks Random access memory Signal processing single instruction multiple data (SIMD) architecture Software algorithms SRAM Static random access memory Throughput
ISSN:	0018-9200, 1558-173X
Online-Zugang:	Volltext
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