A 28-nm Compute SRAM With Bit-Serial Logic/Arithmetic Operations for Programmable In-Memory Vector Computing

This article proposes a general-purpose hybrid in-/near-memory compute SRAM (CRAM) that combines an 8T transposable bit cell with vector-based, bit-serial in-memory arithmetic to accommodate a wide range of bit-widths, from single to 32 or 64 bits, as well as a complete set of operation types, inclu...

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Vydáno v:IEEE journal of solid-state circuits Ročník 55; číslo 1; s. 76 - 86
Hlavní autoři: Wang, Jingcheng, Wang, Xiaowei, Eckert, Charles, Subramaniyan, Arun, Das, Reetuparna, Blaauw, David, Sylvester, Dennis
Médium: Journal Article
Jazyk:angličtina
Vydáno: New York IEEE 01.01.2020
The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Témata:
8T transposable bit cell
Algorithms
Arithmetic
Bandwidth
bit-serial arithmetic
CMOS
Computer architecture
flexible bit-width
Floating point arithmetic
in-memory computing (IMC)
Internet of Things
memory
Microprocessors
Multiplication
near-memory computing
Neural networks
Random access memory
Signal processing
single instruction multiple data (SIMD) architecture
Software algorithms
SRAM
Static random access memory
Throughput
ISSN:0018-9200, 1558-173X
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Shrnutí:This article proposes a general-purpose hybrid in-/near-memory compute SRAM (CRAM) that combines an 8T transposable bit cell with vector-based, bit-serial in-memory arithmetic to accommodate a wide range of bit-widths, from single to 32 or 64 bits, as well as a complete set of operation types, including integer and floating-point addition, multiplication, and division. This approach provides the flexibility and programmability necessary for evolving software algorithms ranging from neural networks to graph and signal processing. The proposed design was implemented in a small Internet of Things (IoT) processor in the 28-nm CMOS consisting of a Cortex-M0 CPU and 8 CRAM banks of 16 kB each (128 kB total). The system achieves 475-MHz operation at 1.1 V and, with all CRAMs active, produces 30 GOPS or 1.4 GFLOPS on 32-bit operands. It achieves an energy efficiency of 0.56 TOPS/W for 8-bit multiplication and 5.27 TOPS/W for 8-bit addition at 0.6 V and 114 MHz.
Bibliografie:ObjectType-Article-1
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content type line 14
ISSN:0018-9200
1558-173X
DOI:10.1109/JSSC.2019.2939682