A 28-nm Compute SRAM With Bit-Serial Logic/Arithmetic Operations for Programmable In-Memory Vector Computing
This article proposes a general-purpose hybrid in-/near-memory compute SRAM (CRAM) that combines an 8T transposable bit cell with vector-based, bit-serial in-memory arithmetic to accommodate a wide range of bit-widths, from single to 32 or 64 bits, as well as a complete set of operation types, inclu...
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| Veröffentlicht in: | IEEE journal of solid-state circuits Jg. 55; H. 1; S. 76 - 86 |
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| Sprache: | Englisch |
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01.01.2020
The Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
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| Abstract | This article proposes a general-purpose hybrid in-/near-memory compute SRAM (CRAM) that combines an 8T transposable bit cell with vector-based, bit-serial in-memory arithmetic to accommodate a wide range of bit-widths, from single to 32 or 64 bits, as well as a complete set of operation types, including integer and floating-point addition, multiplication, and division. This approach provides the flexibility and programmability necessary for evolving software algorithms ranging from neural networks to graph and signal processing. The proposed design was implemented in a small Internet of Things (IoT) processor in the 28-nm CMOS consisting of a Cortex-M0 CPU and 8 CRAM banks of 16 kB each (128 kB total). The system achieves 475-MHz operation at 1.1 V and, with all CRAMs active, produces 30 GOPS or 1.4 GFLOPS on 32-bit operands. It achieves an energy efficiency of 0.56 TOPS/W for 8-bit multiplication and 5.27 TOPS/W for 8-bit addition at 0.6 V and 114 MHz. |
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| AbstractList | This article proposes a general-purpose hybrid in-/near-memory compute SRAM (CRAM) that combines an 8T transposable bit cell with vector-based, bit-serial in-memory arithmetic to accommodate a wide range of bit-widths, from single to 32 or 64 bits, as well as a complete set of operation types, including integer and floating-point addition, multiplication, and division. This approach provides the flexibility and programmability necessary for evolving software algorithms ranging from neural networks to graph and signal processing. The proposed design was implemented in a small Internet of Things (IoT) processor in the 28-nm CMOS consisting of a Cortex-M0 CPU and 8 CRAM banks of 16 kB each (128 kB total). The system achieves 475-MHz operation at 1.1 V and, with all CRAMs active, produces 30 GOPS or 1.4 GFLOPS on 32-bit operands. It achieves an energy efficiency of 0.56 TOPS/W for 8-bit multiplication and 5.27 TOPS/W for 8-bit addition at 0.6 V and 114 MHz. |
| Author | Das, Reetuparna Blaauw, David Subramaniyan, Arun Wang, Xiaowei Eckert, Charles Sylvester, Dennis Wang, Jingcheng |
| Author_xml | – sequence: 1 givenname: Jingcheng orcidid: 0000-0001-5831-9063 surname: Wang fullname: Wang, Jingcheng email: jiwang@umich.edu organization: Department of Electrical Engineering and Computer Science, University of Michigan, Ann Arbor, MI, USA – sequence: 2 givenname: Xiaowei orcidid: 0000-0002-5883-7327 surname: Wang fullname: Wang, Xiaowei organization: Department of Electrical Engineering and Computer Science, University of Michigan, Ann Arbor, MI, USA – sequence: 3 givenname: Charles orcidid: 0000-0002-8839-9890 surname: Eckert fullname: Eckert, Charles organization: Department of Electrical Engineering and Computer Science, University of Michigan, Ann Arbor, MI, USA – sequence: 4 givenname: Arun orcidid: 0000-0001-6119-3182 surname: Subramaniyan fullname: Subramaniyan, Arun organization: Department of Electrical Engineering and Computer Science, University of Michigan, Ann Arbor, MI, USA – sequence: 5 givenname: Reetuparna surname: Das fullname: Das, Reetuparna organization: Department of Electrical Engineering and Computer Science, University of Michigan, Ann Arbor, MI, USA – sequence: 6 givenname: David orcidid: 0000-0001-6744-7075 surname: Blaauw fullname: Blaauw, David organization: Department of Electrical Engineering and Computer Science, University of Michigan, Ann Arbor, MI, USA – sequence: 7 givenname: Dennis orcidid: 0000-0003-2598-0458 surname: Sylvester fullname: Sylvester, Dennis organization: Department of Electrical Engineering and Computer Science, University of Michigan, Ann Arbor, MI, USA |
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| Cites_doi | 10.1109/CVPR.2016.90 10.1145/216585.216588 10.1109/ISSCC.2019.8662419 10.1109/CICC.1992.591879 10.1109/ISCA.2018.00015 10.1038/nature14539 10.1109/JSSC.2018.2871623 10.1109/JSSC.2017.2782087 10.1109/JSSC.2016.2642198 10.1109/CICC.2017.7993629 10.1109/JSSC.2017.2776302 10.1109/JSSC.2019.2899730 10.1109/JSSC.2018.2880918 10.1109/TC.1982.1676015 10.1109/JSSC.2016.2515510 10.1109/JSSC.2017.2776309 10.1109/HPCA.2016.7446049 10.1145/3140659.3080246 10.1109/JSSC.2018.2841824 10.1109/JSSC.2018.2885559 10.1109/JSSC.2018.2865489 10.1109/ICRC.2016.7738698 10.1109/ISCA.2018.00040 10.1109/ISSCC.2019.8662435 10.1109/JSSC.2013.2258815 10.1145/3123939.3123977 |
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| References | ref35 ref13 jia (ref18) 2018 ref15 ref36 ref14 ref31 ref11 denyer (ref26) 1985 ref10 ref2 ref1 ref17 horowitz (ref5) 2014 ref16 ref19 lecun (ref6) 2015; 521 krizhevsky (ref34) 2012 smets (ref9) 2019 ref23 ref25 ref20 (ref33) 2018 ref22 ref21 jeloka (ref24) 2016; 51 ref28 ref27 ref29 chen (ref12) 2018 ref8 ref7 seo (ref30) 2011 ref4 ref3 (ref32) 2017 |
| References_xml | – ident: ref7 doi: 10.1109/CVPR.2016.90 – year: 2017 ident: ref32 publication-title: ARM Cortex-M Series – start-page: 44 year: 2019 ident: ref9 article-title: A 978GOPS/W flexible streaming processor for real-time image processing applications in 22 nm FDSOI publication-title: IEEE ISSCC Dig Tech Papers – ident: ref1 doi: 10.1145/216585.216588 – ident: ref21 doi: 10.1109/ISSCC.2019.8662419 – ident: ref3 doi: 10.1109/CICC.1992.591879 – ident: ref20 doi: 10.1109/ISCA.2018.00015 – year: 2018 ident: ref33 publication-title: Cuda-convnet – volume: 521 start-page: 436 year: 2015 ident: ref6 article-title: Deep learning publication-title: Nature doi: 10.1038/nature14539 – ident: ref28 doi: 10.1109/JSSC.2018.2871623 – ident: ref16 doi: 10.1109/JSSC.2017.2782087 – ident: ref14 doi: 10.1109/JSSC.2016.2642198 – ident: ref13 doi: 10.1109/CICC.2017.7993629 – ident: ref22 doi: 10.1109/JSSC.2017.2776302 – start-page: 1 year: 2011 ident: ref30 article-title: A 45 nm CMOS neuromorphic chip with a scalable architecture for learning in networks of spiking neurons publication-title: Proc IEEE Custom Integr Circuits Conf (CICC) – start-page: 10 year: 2014 ident: ref5 article-title: Computing's energy problem (and what we can do about it) publication-title: IEEE ISSCC Dig Tech Papers – ident: ref19 doi: 10.1109/JSSC.2019.2899730 – year: 1985 ident: ref26 publication-title: VLSI Signal Processing A Bit-Serial Approach – ident: ref15 doi: 10.1109/JSSC.2018.2880918 – ident: ref25 doi: 10.1109/TC.1982.1676015 – volume: 51 start-page: 1009 year: 2016 ident: ref24 article-title: A 28 nm configurable memory (TCAM/BCAM/SRAM) using push-rule 6T bit cell enabling logic-in-memory publication-title: IEEE J Solid-State Circuits doi: 10.1109/JSSC.2016.2515510 – ident: ref23 doi: 10.1109/JSSC.2017.2776309 – start-page: 494 year: 2018 ident: ref12 article-title: A 65 nm 1 Mb nonvolatile computing-in-memory ReRAM macro with sub-16 ns multiply-and-accumulate for binary DNN AI edge processors publication-title: IEEE Int Solid-State Circuits Conf (ISSCC) Dig Tech Papers – ident: ref11 doi: 10.1109/HPCA.2016.7446049 – ident: ref4 doi: 10.1145/3140659.3080246 – ident: ref36 doi: 10.1109/JSSC.2018.2841824 – ident: ref8 doi: 10.1109/JSSC.2018.2885559 – ident: ref27 doi: 10.1109/JSSC.2018.2865489 – ident: ref29 doi: 10.1109/ICRC.2016.7738698 – ident: ref31 doi: 10.1109/ISCA.2018.00040 – ident: ref17 doi: 10.1109/ISSCC.2019.8662435 – ident: ref35 doi: 10.1109/ISCA.2018.00040 – start-page: 1097 year: 2012 ident: ref34 article-title: Imagenet classification with deep convolutional neural networks publication-title: Proc Adv Neural Inf Process Syst (NIPS) – ident: ref2 doi: 10.1109/JSSC.2013.2258815 – ident: ref10 doi: 10.1145/3123939.3123977 – year: 2018 ident: ref18 article-title: A microprocessor implemented in 65 nm CMOS with configurable and bit-scalable accelerator for programmable in-memory computing publication-title: arXiv 1811 04047 |
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| SubjectTerms | 8T transposable bit cell Algorithms Arithmetic Bandwidth bit-serial arithmetic CMOS Computer architecture flexible bit-width Floating point arithmetic in-memory computing (IMC) Internet of Things memory Microprocessors Multiplication near-memory computing Neural networks Random access memory Signal processing single instruction multiple data (SIMD) architecture Software algorithms SRAM Static random access memory Throughput |
| Title | A 28-nm Compute SRAM With Bit-Serial Logic/Arithmetic Operations for Programmable In-Memory Vector Computing |
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