Wang, J., Wang, X., Eckert, C., Subramaniyan, A., Das, R., Blaauw, D., & Sylvester, D. (2020). A 28-nm Compute SRAM With Bit-Serial Logic/Arithmetic Operations for Programmable In-Memory Vector Computing. IEEE journal of solid-state circuits, 55(1), 76-86. https://doi.org/10.1109/JSSC.2019.2939682
Citace podle Chicago (17th ed.)Wang, Jingcheng, Xiaowei Wang, Charles Eckert, Arun Subramaniyan, Reetuparna Das, David Blaauw, a Dennis Sylvester. "A 28-nm Compute SRAM With Bit-Serial Logic/Arithmetic Operations for Programmable In-Memory Vector Computing." IEEE Journal of Solid-state Circuits 55, no. 1 (2020): 76-86. https://doi.org/10.1109/JSSC.2019.2939682.
Citace podle MLA (9th ed.)Wang, Jingcheng, et al. "A 28-nm Compute SRAM With Bit-Serial Logic/Arithmetic Operations for Programmable In-Memory Vector Computing." IEEE Journal of Solid-state Circuits, vol. 55, no. 1, 2020, pp. 76-86, https://doi.org/10.1109/JSSC.2019.2939682.