Embedded 1-Mb ReRAM-Based Computing-in- Memory Macro With Multibit Input and Weight for CNN-Based AI Edge Processors

Computing-in-memory (CIM) based on embedded nonvolatile memory is a promising candidate for energy-efficient multiply-and-accumulate (MAC) operations in artificial intelligence (AI) edge devices. However, circuit design for NVM-based CIM (nvCIM) imposes a number of challenges, including an area-late...

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Veröffentlicht in:IEEE journal of solid-state circuits Jg. 55; H. 1; S. 203 - 215
Hauptverfasser: Xue, Cheng-Xin, Chen, Wei-Hao, Liu, Je-Syu, Li, Jia-Fang, Lin, Wei-Yu, Lin, Wei-En, Wang, Jing-Hong, Wei, Wei-Chen, Huang, Tsung-Yuan, Chang, Ting-Wei, Chang, Tung-Cheng, Kao, Hui-Yao, Chiu, Yen-Cheng, Lee, Chun-Ying, King, Ya-Chin, Lin, Chrong-Jung, Liu, Ren-Shuo, Hsieh, Chih-Cheng, Tang, Kea-Tiong, Chang, Meng-Fan
Format: Journal Article
Sprache:Englisch
Veröffentlicht: New York IEEE 01.01.2020
The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Schlagworte:
Artificial intelligence
Artificial intelligence (AI)
Circuit design
CNN edge processors
Common Information Model (computing)
Computation
computing-in-memory (CIM)
Energy efficiency
Kernel
Nonvolatile memory
Periodic structures
Program processors
ReRAM
Resistance
sense amplifier
Sense amplifiers
Weight
ISSN:0018-9200, 1558-173X
Online-Zugang:Volltext
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Zusammenfassung:Computing-in-memory (CIM) based on embedded nonvolatile memory is a promising candidate for energy-efficient multiply-and-accumulate (MAC) operations in artificial intelligence (AI) edge devices. However, circuit design for NVM-based CIM (nvCIM) imposes a number of challenges, including an area-latency-energy tradeoff for multibit MAC operations, pattern-dependent degradation in signal margin, and small read margin. To overcome these challenges, this article proposes the following: 1) a serial-input non-weighted product (SINWP) structure; 2) a down-scaling weighted current translator (DSWCT) and positive-negative current-subtractor (PN-ISUB); 3) a current-aware bitline clamper (CABLC) scheme; and 4) a triple-margin small-offset current-mode sense amplifier (TMCSA). A 55-nm 1-Mb ReRAM-CIM macro was fabricated to demonstrate the MAC operation of 2-b-input, 3-b-weight with 4-b-out. This nvCIM macro achieved <inline-formula> <tex-math notation="LaTeX">T_{\text {MAC}}= 14.6 </tex-math></inline-formula> ns at 4-b-out with peak energy efficiency of 53.17 TOPS/W.
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ISSN:0018-9200
1558-173X
DOI:10.1109/JSSC.2019.2951363