Hardware implementation of a strong pseudorandom number generator based block‐cipher system for color image encryption and decryption

Summary This paper proposed a hardware architecture of a strong block‐cipher system dedicated to digital image encryption and decryption. On the one hand, a pseudorandom number generator (PRNG) based on two 3D chaotic systems is created to produce strong keys. On the other hand, a robust algorithm i...

Ausführliche Beschreibung

Gespeichert in:
Bibliographische Detailangaben
Veröffentlicht in:International journal of circuit theory and applications Jg. 51; H. 1; S. 410 - 436
Hauptverfasser: Gafsi, Mohamed, Amdouni, Rim, Hajjaji, Mohamed Ali, Mtibaa, Abdellatif, Bourennane, El‐Bey
Format: Journal Article
Sprache:Englisch
Veröffentlicht: Bognor Regis Wiley Subscription Services, Inc 01.01.2023
Schlagworte:
Algorithms
block‐cipher
chaos
Color imagery
Complexity
Digital imaging
Encryption
Field programmable gate arrays
FPGA
Hardware
Permutations
Pixels
PRNG
Pseudorandom
security level
throughput
ISSN:0098-9886, 1097-007X
Online-Zugang:Volltext
Tags: Tag hinzufügen
Keine Tags, Fügen Sie den ersten Tag hinzu!
Beschreibung
Zusammenfassung:Summary This paper proposed a hardware architecture of a strong block‐cipher system dedicated to digital image encryption and decryption. On the one hand, a pseudorandom number generator (PRNG) based on two 3D chaotic systems is created to produce strong keys. On the other hand, a robust algorithm is proposed to ensure high‐level security and low computational complexity of image encryption. The algorithm performs image encryption mainly through three processes: pixel values hiding by applying the XOR operation with a key, pixel positions hiding by operating random permutation, and pixel substitution using the S‐box method. To increase the complexity, R rounds of encryption could be accomplished in a loop. Then as a final step, using the Xilinx Vivado/system generator tool, the hardware cryptosystem is developed, implemented, and evaluated on an FPGA‐Zynq evaluation board. According to the synthesis results, the suggested hardware system performs on a reduced FPGA area and gives a good frequency of 156.813 MHz with a high throughput of 20,072.064 Mbps. Several tools and tests utilizing various images are used to evaluate and analyze the hardware cryptosystem. The experimental results show that the hardware implementation has higher performance compared to other recent works. This paper proposed a hardware architecture of a strong block‐cipher system for digital image encryption and decryption. A PRNG based on two 3D chaotic systems is created to produce strong keys. While, the algorithm performs image encryption through three processes: pixels values hiding, pixels positions hiding, and pixels substitution. To increase the complexity, R rounds of encryption are performed. The hardware cryptosystem is implemented on an FPGA‐Zynq board maintaining a frequency of 156.813 MHz and high throughput of 20,072.064 Mbps.
Bibliographie:Mohamed Gafsi, Rim Amdouni, Mohamed Ali Hajjaji, Abdellatif Mtibaa, and El‐Bay Bourennane are equally contributing authors.
ObjectType-Article-1
SourceType-Scholarly Journals-1
ObjectType-Feature-2
content type line 14
ISSN:0098-9886
1097-007X
DOI:10.1002/cta.3415