Parallel Nonlinear Model Predictive Controller for Real-Time Path Tracking of Autonomous Vehicle

To raise the real-time performance of the path tracking controller based on nonlinear model predictive control (NMPC), this article presents a parallel NMPC controller based on Newton optimization algorithm and field programmable gate array (FPGA) implementation for path tracking control of autonomo...

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Vydáno v:IEEE transactions on industrial electronics (1982) Ročník 71; číslo 12; s. 16503 - 16513
Hlavní autoři: Xu, Fang, Zhang, Xu, Chen, Hong, Hu, Yunfeng, Wang, Ping, Qu, Ting
Médium: Journal Article
Jazyk:angličtina
Vydáno: New York IEEE 01.12.2024
The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Témata:
Acceleration
Algorithms
Autonomous vehicles
Control systems design
Controllers
Coupling
Design optimization
Field programmable gate array (FPGA) implementation
Field programmable gate arrays
Hardware
Mathematical models
Nonlinear control
Nonlinear dynamics
nonlinear model predictive control
parallel Newton optimization algorithm
Path tracking
path tracking control
Performance prediction
Predictive control
Predictive models
Real time
Real-time systems
Tracking
Tracking control
Vehicle dynamics
Wheels
ISSN:0278-0046, 1557-9948
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Shrnutí:To raise the real-time performance of the path tracking controller based on nonlinear model predictive control (NMPC), this article presents a parallel NMPC controller based on Newton optimization algorithm and field programmable gate array (FPGA) implementation for path tracking control of autonomous vehicle. First, a nonlinear vehicle dynamics model is established to represent the nonlinear and coupling properties of vehicle system, and an integrated NMPC controller relies that on a single controller is designed for path tracking. Second, software and hardware parallel calculations are utilized to accelerate the online computation speed of NMPC controller. One is using a parallel Newton algorithm to reduce the complexity of the NMPC optimization problem by utilizing reasonable approximations of the coupling variables to break down the recursion process. The other one is the FPGA hardware acceleration of NMPC. Through analyzing different FPGA design schemes, the most suitable implementation is chosen with the tradeoff between hardware resource and achievable speed. Finally, simulations and hardware-in-the-loop experiment are conducted to validate the effectiveness and real-time performance of the proposed parallel NMPC path tracking controller.
Bibliografie:ObjectType-Article-1
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content type line 14
ISSN:0278-0046
1557-9948
DOI:10.1109/TIE.2024.3390738