An Accurate Process-Induced Variability-Aware Compact Model-Based Circuit Performance Estimation for Design-Technology Co-Optimization

In sub-10-nm fin field-effect transistors (FinFETs), line-edge roughness (LER) and metal-gate granularity (MGG) are the two most dominant sources of variability and are mostly modeled semi-empirically. In this work, compact models of LER and MGG are used. We show an accurate process-induced variabil...

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Vydáno v:	IEEE transactions on electron devices Ročník 69; číslo 1; s. 45 - 50
Hlavní autoři:	Patil, Shubham, Rawat, Amita, Ganguly, Udayan
Médium:	Journal Article
Jazyk:	angličtina
Vydáno:	New York IEEE 01.01.2022 The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Témata:	Accuracy Berkeley short-channel igfet model–common multi-gate (BSIM-CMG) Calibration Circuit design Data models Design optimization design-technology co-optimization (DTCO) Estimation Field effect transistors fin field-effect transistor (FinFET) Integrated circuit modeling line-edge roughness (LER) Metal oxide semiconductors metal-gate granularity (MGG) Model accuracy Performance evaluation process-induced variability (PIV) Random access memory Semiconductor devices simulation program with integrated circuit emphasis (SPICE) simulation SPICE Static random access memory static random-access memory (SRAM) technology computer-aided design (TCAD) Variability
ISSN:	0018-9383, 1557-9646
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