An Accurate Process-Induced Variability-Aware Compact Model-Based Circuit Performance Estimation for Design-Technology Co-Optimization

In sub-10-nm fin field-effect transistors (FinFETs), line-edge roughness (LER) and metal-gate granularity (MGG) are the two most dominant sources of variability and are mostly modeled semi-empirically. In this work, compact models of LER and MGG are used. We show an accurate process-induced variabil...

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Vydané v:IEEE transactions on electron devices Ročník 69; číslo 1; s. 45 - 50
Hlavní autori: Patil, Shubham, Rawat, Amita, Ganguly, Udayan
Médium: Journal Article
Jazyk:English
Vydavateľské údaje: New York IEEE 01.01.2022
The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Predmet:
Accuracy
Berkeley short-channel igfet model–common multi-gate (BSIM-CMG)
Calibration
Circuit design
Data models
Design optimization
design-technology co-optimization (DTCO)
Estimation
Field effect transistors
fin field-effect transistor (FinFET)
Integrated circuit modeling
line-edge roughness (LER)
Metal oxide semiconductors
metal-gate granularity (MGG)
Model accuracy
Performance evaluation
process-induced variability (PIV)
Random access memory
Semiconductor devices
simulation program with integrated circuit emphasis (SPICE) simulation
SPICE
Static random access memory
static random-access memory (SRAM)
technology computer-aided design (TCAD)
Variability
ISSN:0018-9383, 1557-9646
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Popis
Shrnutí:In sub-10-nm fin field-effect transistors (FinFETs), line-edge roughness (LER) and metal-gate granularity (MGG) are the two most dominant sources of variability and are mostly modeled semi-empirically. In this work, compact models of LER and MGG are used. We show an accurate process-induced variability (PIV)-aware compact model-based circuit performance estimation for design-technology co-optimization (DTCO). This work is carried out using an experimentally validated Berkeley Short-channel IGFET Model-Common Multi-Gate (BSIM-CMG) model on a 7-nm FinFET node. First, we have shown performance benchmarking of LER and MGG models with the state of the art and shown <inline-formula> <tex-math notation="LaTeX">\sim 4\times </tex-math></inline-formula> (<inline-formula> <tex-math notation="LaTeX">\sim 2.3\times </tex-math></inline-formula>) accuracy improvement for nMOS (pMOS) in the estimation of device figure of merits (DFoMs). Second, ring oscillator (RO) and static random-access memory (SRAM) circuit's performance estimation is carried out for LER and MGG variability. Furthermore, ~22% more optimistic estimate of (<inline-formula> <tex-math notation="LaTeX">\sigma /\mu </tex-math></inline-formula>) SHM (static hold margin) compared to the state-of-the-art model with <inline-formula> <tex-math notation="LaTeX">{V}_{\text {DD}} </tex-math></inline-formula> variation is shown. Finally, we demonstrate our improved DFoM accuracy translated to more accurate circuit figure of merits (CFoMs) performance estimation. For worst-case SHM (3(<inline-formula> <tex-math notation="LaTeX">\sigma /\mu </tex-math></inline-formula>) SHM @<inline-formula> <tex-math notation="LaTeX">{V}_{\text {DD}}={0.75} </tex-math></inline-formula> V) compared to state of the art, dynamic (standby) power reduction by ~73% (~61%) is shown. Thus, our enhanced variability model accuracy enables more credible DTCO with significantly better performance estimates.
Bibliografia:ObjectType-Article-1
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ISSN:0018-9383
1557-9646
DOI:10.1109/TED.2021.3131966