A Fast DVM Algorithm for Wideband Time-Delay Multi-Beam Beamformers
This paper presents a sparse factorization for the delay Vandermonde matrix (DVM) along with fast, exact, radix-2, and recursive algorithms to compute the DVM-vector product for wideband multi-beam antenna arrays. The proposed algorithms enable low-complexity wideband beamformers in emerging millime...
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| Veröffentlicht in: | IEEE transactions on signal processing Jg. 70; S. 1 - 13 |
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| Hauptverfasser: | , , , , |
| Format: | Journal Article |
| Sprache: | Englisch |
| Veröffentlicht: |
New York
IEEE
01.01.2022
The Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Schlagworte: | |
| ISSN: | 1053-587X, 1941-0476 |
| Online-Zugang: | Volltext |
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| Zusammenfassung: | This paper presents a sparse factorization for the delay Vandermonde matrix (DVM) along with fast, exact, radix-2, and recursive algorithms to compute the DVM-vector product for wideband multi-beam antenna arrays. The proposed algorithms enable low-complexity wideband beamformers in emerging millimeter-wave wireless communication networks by reducing the complexity of <inline-formula><tex-math notation="LaTeX">N</tex-math></inline-formula>-beam wideband beamforming from <inline-formula><tex-math notation="LaTeX">\mathcal {O}(N^{2})</tex-math></inline-formula> to <inline-formula><tex-math notation="LaTeX">\mathcal {O}(N \mathrm{\: log\:} N)</tex-math></inline-formula>, where <inline-formula><tex-math notation="LaTeX">N=2^{r}(r \geq 1)</tex-math></inline-formula>. As a result, the algorithms are faster than the brute-force computation of the DVM-vector product and more efficient than the direct realization of true-time-delay-based multi-beam beamformers. The proposed low-complexity algorithms' signal flow graph (SFG) is also presented to highlight their suitability for hardware implementations. The 2-D frequency responses of DVM-based beamformers are explained through an array signal processing example. Simulation results suggest that integrated circuit (IC) implementations of the SFG significantly reduce chip area and power consumption. |
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| Bibliographie: | ObjectType-Article-1 SourceType-Scholarly Journals-1 ObjectType-Feature-2 content type line 14 |
| ISSN: | 1053-587X 1941-0476 |
| DOI: | 10.1109/TSP.2022.3231182 |