Artificial Neural Network-Based Compact Modeling Methodology for Advanced Transistors

The artificial neural network (ANN)-based compact modeling methodology is evaluated in the context of advanced field-effect transistor (FET) modeling for Design-Technology-Cooptimization (DTCO) and pathfinding activities. An ANN model architecture for FETs is introduced, and the results clearly show...

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Vydané v:IEEE transactions on electron devices Ročník 68; číslo 3; s. 1318 - 1325
Hlavní autori: Wang, Jing, Kim, Yo-Han, Ryu, Jisu, Jeong, Changwook, Choi, Woosung, Kim, Daesin
Médium: Journal Article
Jazyk:English
Vydavateľské údaje: New York IEEE 01.03.2021
The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
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ISSN:0018-9383, 1557-9646
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Shrnutí:The artificial neural network (ANN)-based compact modeling methodology is evaluated in the context of advanced field-effect transistor (FET) modeling for Design-Technology-Cooptimization (DTCO) and pathfinding activities. An ANN model architecture for FETs is introduced, and the results clearly show that by carefully choosing the conversion functions (i.e., from ANN outputs to device terminal currents or charges) and the loss functions for ANN training, ANN models can reproduce the current-voltage and charge-voltage characteristics of advanced FETs with excellent accuracy. A few key techniques are introduced in this work to enhance the capabilities of ANN models (e.g., model retargeting, variability modeling) and to improve ANN training efficiency and SPICE simulation turn-around-time (TAT). A systematical study on the impact of the ANN size on ANN model accuracy and SPICE simulation TAT is conducted, and an automated flow for generating optimum ANN models is proposed. The findings in this work suggest that the ANN-based methodology can be a promising compact modeling solution for advanced DTCO and pathfinding activities.
Bibliografia:ObjectType-Article-1
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content type line 14
ISSN:0018-9383
1557-9646
DOI:10.1109/TED.2020.3048918