An Optimal Algorithm for Scheduling Requests on Interleaved Memories for a Pipelined Processor

In this paper an optimal algorithm for scheduling requests on interleaved memories is presented. With this algorithm the average completion time for servicing a finite set of randomly generated requests is proved to be minimum. Performance of this algorithm for nonrandom requests has not been proved...

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Bibliographic Details
Published in:IEEE transactions on computers Vol. C-30; no. 10; pp. 787 - 800
Main Authors: Ramamoorthy, C V, Wah, B W
Format: Journal Article
Language:English
Published: IEEE 01.10.1981
Subjects:
Bandwidth
Computers
Costs
Data modules
instruction modules
intelligent buffers
interleaved memories
memory bandwidth
Memory management
Memory modules
optimal scheduling algorithm
Organizations
pipelined processor
Random access memory
Scheduling
Scheduling algorithms
Simulation
ISSN:0018-9340, 1557-9956
Online Access:Get full text
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Summary:In this paper an optimal algorithm for scheduling requests on interleaved memories is presented. With this algorithm the average completion time for servicing a finite set of randomly generated requests is proved to be minimum. Performance of this algorithm for nonrandom requests has not been proved. However, it is compared with alternate algorithms using simulations. A pipelined processor is used as an example for the generation of nonrandom requests to the memories. Nonetheless, the source could have been a vector processor or a multiprocessor system. Two alternative organizations are investigated, one with a common set of fixed size buffers to store conflicting requests and one with individual fixed size buffers for each module. These two organizations are shown to be equivalent as far as the average utilization and waiting cycles are concerned. An intelligent scheduler determines the order of initiation of the memory modules. An alternative design with separate instruction and data modules is investigated. It is found that separation gains very little in performance because of the unequal rates of access to the instruction and the data modules. The basic assumptions for the analysis are that the dependency effects are ignored and the request rate is very high so that any empty buffers can be filled immediately. The degradation in memory utilization due to dependency effects is studied in a separate paper in this issue.
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ISSN:0018-9340
1557-9956
DOI:10.1109/TC.1981.1675697