A Parallel and Updatable Architecture for FPGA-Based Packet Classification With Large-Scale Rule Sets

As a programmable hardware, field-programmable gate array (FPGA) provides more opportunities for algorithmic network packet classification. Despite more than 10 years of research, the most actively investigated pipeline architectures still struggle to support fast rule search and efficient rule upda...

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Veröffentlicht in:	IEEE MICRO Jg. 43; H. 2; S. 110 - 119
Hauptverfasser:	Xin, Yao, Li, Wenjun, Xie, Gaogang, Xu, Yang, Wang, Yi
Format:	Journal Article
Sprache:	Englisch
Veröffentlicht:	Los Alamitos IEEE 01.03.2023 The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Schlagworte:	Classification Classification algorithms Computer architecture Field programmable gate arrays Hardware Modular design Packets (communication) Pipelines Pipelining (computers) Random forests Searching Throughput
ISSN:	0272-1732, 1937-4143
Online-Zugang:	Volltext
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