A Parallel and Updatable Architecture for FPGA-Based Packet Classification With Large-Scale Rule Sets

As a programmable hardware, field-programmable gate array (FPGA) provides more opportunities for algorithmic network packet classification. Despite more than 10 years of research, the most actively investigated pipeline architectures still struggle to support fast rule search and efficient rule upda...

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Vydané v:IEEE MICRO Ročník 43; číslo 2; s. 110 - 119
Hlavní autori: Xin, Yao, Li, Wenjun, Xie, Gaogang, Xu, Yang, Wang, Yi
Médium: Journal Article
Jazyk:English
Vydavateľské údaje: Los Alamitos IEEE 01.03.2023
The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
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ISSN:0272-1732, 1937-4143
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Shrnutí:As a programmable hardware, field-programmable gate array (FPGA) provides more opportunities for algorithmic network packet classification. Despite more than 10 years of research, the most actively investigated pipeline architectures still struggle to support fast rule search and efficient rule update for large-scale rule sets. In this article, we design and implement a novel architecture for multitree-based packet classification on FPGA, where the search and update processes are decoupled. A strategy of multi-processing elements (PEs), parallel search, and serial update is adopted. The parsing of multiple tree search results adopts a modular and hierarchical design, supporting architecture with various tree numbers. In addition, incremental rule updates can be achieved simply by traversing all PEs in one pass, with little and bounded impact on rule searching. Compared with TcbTree, the state-of-the-art updatable classifier, the experimental results on FPGA show that the classification performance of our design improves 3.4× on average for various 100k-scale rule sets.
Bibliografia:ObjectType-Article-1
SourceType-Scholarly Journals-1
ObjectType-Feature-2
content type line 14
ISSN:0272-1732
1937-4143
DOI:10.1109/MM.2023.3238012