Xin, Y., Li, W., Xie, G., Xu, Y., & Wang, Y. (2023). A Parallel and Updatable Architecture for FPGA-Based Packet Classification With Large-Scale Rule Sets. IEEE MICRO, 43(2), 110-119. https://doi.org/10.1109/MM.2023.3238012
Citace podle Chicago (17th ed.)Xin, Yao, Wenjun Li, Gaogang Xie, Yang Xu, a Yi Wang. "A Parallel and Updatable Architecture for FPGA-Based Packet Classification With Large-Scale Rule Sets." IEEE MICRO 43, no. 2 (2023): 110-119. https://doi.org/10.1109/MM.2023.3238012.
Citace podle MLA (9th ed.)Xin, Yao, et al. "A Parallel and Updatable Architecture for FPGA-Based Packet Classification With Large-Scale Rule Sets." IEEE MICRO, vol. 43, no. 2, 2023, pp. 110-119, https://doi.org/10.1109/MM.2023.3238012.
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