Application-Guided Power-Efficient Fault Tolerance for H.264 Context Adaptive Variable Length Coding

This paper presents a fault-tolerance technique for H.264's Context-Adaptive Variable Length Coding (CAVLC) on unreliable computing hardware. The application-specific knowledge is leveraged at both algorithm and architecture levels to protect the CAVLC process (especially context adaptation and...

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Vydáno v:IEEE transactions on computers Ročník 66; číslo 4; s. 560 - 574
Hlavní autoři: Shafique, Muhammad, Rehman, Semeen, Kriebel, Florian, Usman Karim Khan, Muhammad, Zatt, Bruno, Subramaniyan, Arun, Boessio Vizzotto, Bruno, Henkel, Jorg
Médium: Journal Article
Jazyk:angličtina
Vydáno: New York IEEE 01.04.2017
The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Témata:
Algorithm design and analysis
Application-specific optimization
Coding
Computer architecture
Encoding
entropy coding
Fault tolerance
Fault tolerant systems
h.264
Hardware
reliability
Syntactics
video coding
Video data
ISSN:0018-9340, 1557-9956
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Shrnutí:This paper presents a fault-tolerance technique for H.264's Context-Adaptive Variable Length Coding (CAVLC) on unreliable computing hardware. The application-specific knowledge is leveraged at both algorithm and architecture levels to protect the CAVLC process (especially context adaptation and coding tables) in a reliable yet power-efficient manner. Specifically, the statistical analysis of coding syntax and video content properties are exploited for: (1) selective redundancy of coefficient/header data of video bitstreams; (2) partitioning the coding tables into various sub-tables to reduce the power overhead of fault tolerance; and (3) run-time power management of memory parts storing the sub-tables and their parity computations. Experimental results demonstrate that leveraging application-specific knowledge reduces area and performance overhead by 2x compared to a double-parity table protection technique. For functional verification and area comparison, the complete H.264 CAVLC architecture is prototyped on a Xilinx Virtex-5 FPGA (though not limited to it).
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ISSN:0018-9340
1557-9956
DOI:10.1109/TC.2016.2616313