RC-NVM: Dual-Addressing Non-Volatile Memory Architecture Supporting Both Row and Column Memory Accesses

Although emerging non-volatile memories (NVMs) have been comprehensively studied to design next-generation memory systems, the symmetry of the crossbar structure adopted by most NVMs has not been addressed. In this work, we argue that crossbar-based NVMs can enable dual-addressing memory architectur...

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Published in:IEEE transactions on computers Vol. 68; no. 2; pp. 239 - 254
Main Authors: Li, Shuo, Xiao, Nong, Wang, Peng, Sun, Guangyu, Wang, Xiaoyang, Chen, Yiran, Li, Hai Helen, Cong, Jason, Zhang, Tao
Format: Journal Article
Language:English
Published: New York IEEE 01.02.2019
The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subjects:
Cache storage
Computer architecture
Computer memory
crossbar
Design engineering
in-memory database
Memory architecture
Non-volatile memory
Nonvolatile memory
OLAP
OLTP
Random access memory
Workloads
ISSN:0018-9340, 1557-9956
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Abstract Although emerging non-volatile memories (NVMs) have been comprehensively studied to design next-generation memory systems, the symmetry of the crossbar structure adopted by most NVMs has not been addressed. In this work, we argue that crossbar-based NVMs can enable dual-addressing memory architecture, i.e., RC-NVM, to support both row- and column-oriented memory accesses for workloads with different access patterns. Through circuit-level analysis, we first prove that such a dual-addressing architecture is only practical with crossbar-based NVMs rather than DRAM. Then, we introduce the RC-NVM architecture from bank, chip and module levels, and propose RC-NVM aware memory controller. We also address the challenges to implement the end-to-end RC-NVM system. Especially, we design a novel protocol to solve the cache synonym problem with very little overhead. Finally, we introduce the deployment of RC-NVM for in-memory databases (IMDBs) and evaluate its performance with IMDBs and well-optimized general matrix multiply (GEMM) workloads. Experimental results show that with only 10 percent area overhead 1) the memory access performance of IMDBs can be improved up to 14.5X, and 2) for GEMM, RC-NVM naturally supports SIMD operations and outperforms the best tiled layout by 19 percent.
AbstractList Although emerging non-volatile memories (NVMs) have been comprehensively studied to design next-generation memory systems, the symmetry of the crossbar structure adopted by most NVMs has not been addressed. In this work, we argue that crossbar-based NVMs can enable dual-addressing memory architecture, i.e., RC-NVM, to support both row- and column-oriented memory accesses for workloads with different access patterns. Through circuit-level analysis, we first prove that such a dual-addressing architecture is only practical with crossbar-based NVMs rather than DRAM. Then, we introduce the RC-NVM architecture from bank, chip and module levels, and propose RC-NVM aware memory controller. We also address the challenges to implement the end-to-end RC-NVM system. Especially, we design a novel protocol to solve the cache synonym problem with very little overhead. Finally, we introduce the deployment of RC-NVM for in-memory databases (IMDBs) and evaluate its performance with IMDBs and well-optimized general matrix multiply (GEMM) workloads. Experimental results show that with only 10 percent area overhead 1) the memory access performance of IMDBs can be improved up to 14.5X, and 2) for GEMM, RC-NVM naturally supports SIMD operations and outperforms the best tiled layout by 19 percent.
Author Wang, Peng
Cong, Jason
Li, Shuo
Li, Hai Helen
Sun, Guangyu
Chen, Yiran
Wang, Xiaoyang
Xiao, Nong
Zhang, Tao
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Cites_doi 10.1109/ISCA.1998.694761
10.1103/PhysRevLett.21.1450
10.1016/j.sse.2016.07.006
10.14778/2824032.2824069
10.1109/LED.2013.2255096
10.7873/DATE.2013.029
10.14778/1687553.1687625
10.1145/2588555.2610502
10.1145/3035918.3054780
10.1016/S0304-3975(01)00410-8
10.1109/ICDE.2011.5767867
10.1145/2882903.2915231
10.1038/s41467-018-03140-z
10.1145/1559845.1559846
10.1109/MICRO.2004.22
10.1145/1555754.1555758
10.1145/3173162.3173177
10.1109/MM.2010.24
10.1145/2213836.2213946
10.1109/ISCA.2012.6237032
10.1109/LCA.2015.2402435
10.1145/2600212.2600213
10.1109/ISCA.1998.694759
10.1145/2024716.2024718
10.1109/IPDPS.2012.89
10.14778/1921071.1921077
10.1145/2830772.2830820
10.1145/1966895.1966900
10.1109/HPCA.2015.7056056
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References ailamaki (ref37) 1999
ref35
ref13
ref12
(ref20) 0
ref36
ref14
ref31
ref33
ref11
ref32
ref10
kawahara (ref19) 2012
abadi (ref38) 2008
ref2
ref1
ref39
(ref16) 0
ref18
jo (ref17) 2014
(ref22) 0
(ref24) 0
ref26
ref25
ref42
ref41
ref21
chent (ref34) 2016
(ref15) 0
ref28
ref8
(ref30) 0
ref7
zyulkyarov (ref27) 2017
ref9
ref4
ref3
binkert (ref29) 2011; 39
ref6
ref5
ref40
(ref23) 0
References_xml – ident: ref35
  doi: 10.1109/ISCA.1998.694761
– ident: ref18
  doi: 10.1103/PhysRevLett.21.1450
– ident: ref1
  doi: 10.1016/j.sse.2016.07.006
– ident: ref3
  doi: 10.14778/2824032.2824069
– year: 2017
  ident: ref27
  article-title: Method for pinning data in large cache in multi-level memory system
– year: 0
  ident: ref30
  article-title: gemmlowp: A small self-contained low-precision GEMM library
– ident: ref12
  doi: 10.1109/LED.2013.2255096
– ident: ref7
  doi: 10.7873/DATE.2013.029
– start-page: 266
  year: 1999
  ident: ref37
  article-title: DBMSs on a modern processor: Where does time go?
  publication-title: Proc 5th Int Conf Very Large Data Bases
– ident: ref39
  doi: 10.14778/1687553.1687625
– year: 0
  ident: ref22
– ident: ref4
  doi: 10.1145/2588555.2610502
– ident: ref8
  doi: 10.1145/3035918.3054780
– year: 0
  ident: ref23
– start-page: 1
  year: 2016
  ident: ref34
  article-title: Bridging the I/O performance gap for big data workloads: A new NVDIMM-based approach
  publication-title: Proc 49th Annu IEEE/ACM Int Symp Microarchitecture
– year: 0
  ident: ref15
  article-title: Intel and Micron produce breakthrough memory technology
– ident: ref26
  doi: 10.1016/S0304-3975(01)00410-8
– ident: ref2
  doi: 10.1109/ICDE.2011.5767867
– ident: ref5
  doi: 10.1145/2882903.2915231
– ident: ref13
  doi: 10.1038/s41467-018-03140-z
– ident: ref40
  doi: 10.1145/1559845.1559846
– year: 0
  ident: ref20
  article-title: DDR3 SDRAM
– ident: ref21
  doi: 10.1109/MICRO.2004.22
– ident: ref10
  doi: 10.1145/1555754.1555758
– year: 0
  ident: ref16
  article-title: Reimagining the data center memory and storage hierarchy
– start-page: 432
  year: 2012
  ident: ref19
  article-title: An 8 Mb multi-layered cross-point ReRAM macro with 443 MB/s write throughput
  publication-title: Proc IEEE Int Solid-State Circuits Conf
– ident: ref31
  doi: 10.1145/3173162.3173177
– ident: ref14
  doi: 10.1109/MM.2010.24
– ident: ref41
  doi: 10.1145/2213836.2213946
– ident: ref33
  doi: 10.1109/ISCA.2012.6237032
– ident: ref28
  doi: 10.1109/LCA.2015.2402435
– start-page: 6.7.1
  year: 2014
  ident: ref17
  article-title: 3D-stackable crossbar resistive memory based on Field Assisted Superlinear Threshold (FAST) selector
  publication-title: Proc IEEE Int Electron Devices Meeting
– ident: ref32
  doi: 10.1145/2600212.2600213
– ident: ref36
  doi: 10.1109/ISCA.1998.694759
– start-page: 967
  year: 2008
  ident: ref38
  article-title: Column-stores versus row-stores: How different are they really?
  publication-title: Proc ACM SIGMOD Int Conf Manage Data
– volume: 39
  start-page: 1
  year: 2011
  ident: ref29
  article-title: The gem5 simulator
  publication-title: ACM SIGARCH Comput Archit News
  doi: 10.1145/2024716.2024718
– year: 0
  ident: ref24
– ident: ref9
  doi: 10.1109/IPDPS.2012.89
– ident: ref42
  doi: 10.14778/1921071.1921077
– ident: ref6
  doi: 10.1145/2830772.2830820
– ident: ref25
  doi: 10.1145/1966895.1966900
– ident: ref11
  doi: 10.1109/HPCA.2015.7056056
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SubjectTerms Cache storage
Computer architecture
Computer memory
crossbar
Design engineering
in-memory database
Memory architecture
Non-volatile memory
Nonvolatile memory
OLAP
OLTP
Random access memory
Workloads
Title RC-NVM: Dual-Addressing Non-Volatile Memory Architecture Supporting Both Row and Column Memory Accesses
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