Multithreaded and Reconvergent Aware Algorithms for Accurate Digital Circuits Reliability Estimation

Until recently, reliability was not considered to be a major design concern for circuit designers, except in the case of space and mission critical applications. However, the aggressive scaling of CMOS devices has significantly affected their reliable operation. Several schemes have been used for mi...

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Vydáno v:IEEE transactions on reliability Ročník 68; číslo 2; s. 514 - 525
Hlavní autoři: Ibrahim, Walid, Ibrahim, Hazem
Médium: Journal Article
Jazyk:angličtina
Vydáno: New York IEEE 01.06.2019
The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Témata:
Algorithms
Circuit design
Circuit reliability
CMOS
Complexity theory
Computer simulation
Design
Design automation
Design parameters
Designers
Digital electronics
Electronic design automation
fault tolerance
heuristic algorithms
Integrated circuit reliability
Logic circuits
Logic gates
parallel processing
Redundancy
reliability
Reliability engineering
Scaling
Simulation
ISSN:0018-9529, 1558-1721
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Shrnutí:Until recently, reliability was not considered to be a major design concern for circuit designers, except in the case of space and mission critical applications. However, the aggressive scaling of CMOS devices has significantly affected their reliable operation. Several schemes have been used for mitigating the scaling effects and maintaining the reliability above a certain threshold. Many of these schemes rely on incorporating different types of redundancy at the device, gate, and system level, which inevitably affect the area, power, and delay parameters. To optimize the tradeoff between these conflicting parameters, an accurate and efficient reliability EDA tool is needed. Such a tool would help circuit designers compare different reliability schemes and select the one that achieves the target reliability margins while having minimum impact on the other design parameters. However, the enormous size and the complexity of today's logic circuits make accurate calculation of the circuit's reliability a very challenging and time-consuming process. This paper introduces a novel, accurate, and efficient algorithm for circuit reliability estimation. The algorithm improves accuracy by taking the effect of reconvergent fan-out nodes into consideration, while improving efficiency by implementing a multithreaded approach for node evaluation. Simulation results show that the proposed algorithm is efficient and more accurate than other reliability estimation algorithms currently proposed in the literature.
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ISSN:0018-9529
1558-1721
DOI:10.1109/TR.2018.2876475