Enhancing High-Level Synthesis Using a Meta-Programming Approach

In today's increasingly heterogeneous compute landscape, there is high demand for design tools that offer seemingly contradictory features: portable programming abstractions that hide underlying architectural detail, and the capability to optimise and exploit architectural features. Our meta-pr...

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Veröffentlicht in:IEEE transactions on computers Jg. 70; H. 12; S. 2043 - 2055
Hauptverfasser: Vandebon, Jessica, de Figueiredo Coutinho, Jose, Luk, Wayne, Nurvitadhi, Eriko
Format: Journal Article
Sprache:Englisch
Veröffentlicht: New York IEEE 01.12.2021
The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Schlagworte:
Codification
Descriptions
Field programmable gate arrays
FPGA
Heterogeneous computing
Heterogeneous networks
High level synthesis
Mapping
meta-programming
Optimization
Programming
Programming environments
Programming languages
Python
Task analysis
ISSN:0018-9340, 1557-9956
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Zusammenfassung:In today's increasingly heterogeneous compute landscape, there is high demand for design tools that offer seemingly contradictory features: portable programming abstractions that hide underlying architectural detail, and the capability to optimise and exploit architectural features. Our meta-programming approach, Artisan, decouples application functionality from optimisation concerns to address the complexity of mapping high-level application descriptions onto heterogeneous platforms from which they are abstracted. With Artisan, application experts focus on algorithmic behaviour, while platform and domain experts focus on optimisation and mapping. Artisan offers complete design-flow orchestration in a unified programming environment based on Python 3 to enable accessible codification of reusable optimisation strategies that can be automatically applied to high-level application descriptions. We have developed and evaluated an Artisan prototype and a set of customised meta-programs used to automatically optimise six case study applications for CPU+FPGA targets. In our experiments, Artisan-optimised designs achieve the same order of magnitude speedup as manually optimised designs compared to corresponding unoptimised software.
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ISSN:0018-9340
1557-9956
DOI:10.1109/TC.2021.3096429