Complete and Improved FPGA Implementation of Classic McEliece

We present the first specification-compliant constant-time FPGA implementation of the Classic McEliece cryptosystem from the third-round of NIST’s Post-Quantum Cryptography standardization process. In particular, we present the first complete implementation including encapsulation and decapsulation...

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Vydáno v:IACR transactions on cryptographic hardware and embedded systems Ročník 2022; číslo 3; s. 71 - 113
Hlavní autoři: Chen, Po-Jen, Chou, Tung, Deshpande, Sanjay, Lahr, Norman, Niederhagen, Ruben, Szefer, Jakub, Wang, Wen
Médium: Journal Article
Jazyk:angličtina
Vydáno: Ruhr-Universität Bochum 08.06.2022
Témata:
Classic McEliece
Code-Based Cryptography
FPGA
Hardware Implementation
Key Encapsulation Mechanism
PQC
ISSN:2569-2925, 2569-2925
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Shrnutí:We present the first specification-compliant constant-time FPGA implementation of the Classic McEliece cryptosystem from the third-round of NIST’s Post-Quantum Cryptography standardization process. In particular, we present the first complete implementation including encapsulation and decapsulation modules as well as key generation with seed expansion. All the hardware modules are parametrizable, at compile time, with security level and performance parameters. As the most time consuming operation of Classic McEliece is the systemization of the public key matrix during key generation, we present and evaluate three new algorithms that can be used for systemization while complying with the specification: hybrid early-abort systemizer (HEA), single-pass early-abort systemizer (SPEA), and dual-pass earlyabort systemizer (DPEA). All of the designs outperform the prior systemizer designs for Classic McEliece by 2.2x to 2.6x in average runtime and by 1.7x to 2.4x in time-area efficiency. We show that our complete Classic McEliece design for example can perform key generation in 5.2 ms to 20 ms, encapsulation in 0.1 ms to 0.5 ms, and decapsulation in 0.7 ms to 1.5 ms for all security levels on an Xlilinx Artix 7 FPGA. The performance can be increased even further at the cost of resources by increasing the level of parallelization using the performance parameters of our design.
ISSN:2569-2925
2569-2925
DOI:10.46586/tches.v2022.i3.71-113