SCAC: Weakly-coupled execution model for massively parallel systems

This work proposes an execution model for massively parallel systems aiming at ensuring the communications overlap by the computations. This model is named SCAC : Synchronous Communication Asynchronous Computation. This weakly-coupled model separates the execution of communication phases from those...

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Vydáno v:Microprocessors and microsystems Ročník 64; s. 128 - 142
Hlavní autoři: Krichene, Hana, Baklouti, Mouna, Marquet, Philippe, Dekeyser, Jean-Luc, Abid, Mohamed
Médium: Journal Article
Jazyk:angličtina
Vydáno: Kidlington Elsevier B.V 01.02.2019
Elsevier BV
Témata:
Computation
Computer simulation
Configurations
Data transfer (computers)
Execution model
FPGA
Massively parallel architecture
Order parameters
Parallel processing
Parallel programming
SoC
Massively parallel architecture
Parallel processing
FPGA
Execution model
SoC
ISSN:0141-9331, 1872-9436
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Shrnutí:This work proposes an execution model for massively parallel systems aiming at ensuring the communications overlap by the computations. This model is named SCAC : Synchronous Communication Asynchronous Computation. This weakly-coupled model separates the execution of communication phases from those of computation in order to facilitate their overlapping, thus covering the data transfer time. To allow the simultaneous execution of these phases, we propose an approach based on three levels : two globally-centralized/locally-distributed hierarchical control levels and a parallel computation level. A generic and parametric implementation of the SCAC model was performed to fit different applications. This implementation allows the designer to choose the system components (from pre-designed ones) and to set its parameters in order to build the adequate SCAC configuration for the target application. An analytical estimation is proposed to predict the execution time of an application running in SCAC mode, in order to facilitate the parallel program design and the SCAC architecture configuration. The SCAC model was validated by simulation, synthesis and implementation on an FPGA platform, with different examples of parallel computing applications. The comparison of the results obtained by the SCAC model with other models has shown its effectiveness in terms of flexibility and speed-up.
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ISSN:0141-9331
1872-9436
DOI:10.1016/j.micpro.2018.06.003