SCAC: Weakly-coupled execution model for massively parallel systems
This work proposes an execution model for massively parallel systems aiming at ensuring the communications overlap by the computations. This model is named SCAC : Synchronous Communication Asynchronous Computation. This weakly-coupled model separates the execution of communication phases from those...
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| Published in: | Microprocessors and microsystems Vol. 64; pp. 128 - 142 |
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| Main Authors: | , , , , |
| Format: | Journal Article |
| Language: | English |
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Elsevier B.V
01.02.2019
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| ISSN: | 0141-9331, 1872-9436 |
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| Abstract | This work proposes an execution model for massively parallel systems aiming at ensuring the communications overlap by the computations. This model is named SCAC : Synchronous Communication Asynchronous Computation. This weakly-coupled model separates the execution of communication phases from those of computation in order to facilitate their overlapping, thus covering the data transfer time. To allow the simultaneous execution of these phases, we propose an approach based on three levels : two globally-centralized/locally-distributed hierarchical control levels and a parallel computation level. A generic and parametric implementation of the SCAC model was performed to fit different applications. This implementation allows the designer to choose the system components (from pre-designed ones) and to set its parameters in order to build the adequate SCAC configuration for the target application. An analytical estimation is proposed to predict the execution time of an application running in SCAC mode, in order to facilitate the parallel program design and the SCAC architecture configuration. The SCAC model was validated by simulation, synthesis and implementation on an FPGA platform, with different examples of parallel computing applications. The comparison of the results obtained by the SCAC model with other models has shown its effectiveness in terms of flexibility and speed-up. |
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| AbstractList | This work proposes an execution model for massively parallel systems aiming at ensuring the communications overlap by the computations. This model is named SCAC : Synchronous Communication Asynchronous Computation. This weakly-coupled model separates the execution of communication phases from those of computation in order to facilitate their overlapping, thus covering the data transfer time. To allow the simultaneous execution of these phases, we propose an approach based on three levels : two globally-centralized/locally-distributed hierarchical control levels and a parallel computation level. A generic and parametric implementation of the SCAC model was performed to fit different applications. This implementation allows the designer to choose the system components (from pre-designed ones) and to set its parameters in order to build the adequate SCAC configuration for the target application. An analytical estimation is proposed to predict the execution time of an application running in SCAC mode, in order to facilitate the parallel program design and the SCAC architecture configuration. The SCAC model was validated by simulation, synthesis and implementation on an FPGA platform, with different examples of parallel computing applications. The comparison of the results obtained by the SCAC model with other models has shown its effectiveness in terms of flexibility and speed-up. |
| Author | Marquet, Philippe Baklouti, Mouna Krichene, Hana Abid, Mohamed Dekeyser, Jean-Luc |
| Author_xml | – sequence: 1 givenname: Hana surname: Krichene fullname: Krichene, Hana email: hana.krichen@gmail.com organization: CRIStAL – INRIA Lille-North Europe labs, University of Lille 1, France – sequence: 2 givenname: Mouna surname: Baklouti fullname: Baklouti, Mouna email: mouna.baklouti@enis.rnu.tn organization: National School of Engineers of Sfax, CES lab University of Sfax, Tunisia – sequence: 3 givenname: Philippe surname: Marquet fullname: Marquet, Philippe email: Philippe.Marquet@univ-lille.fr organization: CRIStAL – INRIA Lille-North Europe labs, University of Lille 1, France – sequence: 4 givenname: Jean-Luc surname: Dekeyser fullname: Dekeyser, Jean-Luc email: jean-luc.dekeyser@univ-lille.fr organization: CRIStAL – INRIA Lille-North Europe labs, University of Lille 1, France – sequence: 5 givenname: Mohamed surname: Abid fullname: Abid, Mohamed email: mohamed.abid@enis.rnu.tn organization: National School of Engineers of Sfax, CES lab University of Sfax, Tunisia |
| BookMark | eNp9kM1LxDAQxYOs4O7qf-Ch4Lk10zT98CAsxS9Y8KDiMaTpFFLbpibdxf73ZqlnTwPDe2_m_TZkNZgBCbkGGgGF9LaNeq1Ga6KYQh7RNKKUnZE15FkcFglLV2RNIYGwYAwuyMa5llLKaRqvSflW7sq74BPlVzeHyhzGDusAf1AdJm2GoDc1dkFjbNBL5_QRuzkYpZVd59dudhP27pKcN7JzePU3t-Tj8eG9fA73r08v5W4fqjhnUyh5VnCMVaLyFFilKpXwBihWFQdWV01B_XuJ9BUQmkJCkWQq49ggL-omk8C25GbJ9VW_D-gm0ZqDHfxJEUOWQ8xZflIli0pZ45zFRoxW99LOAqg44RKtWHCJEy5BU-Fxedv9YkPf4KjRCqc0DgprbVFNojb6_4Bf4tB29A |
| Cites_doi | 10.1016/j.micpro.2004.01.002 10.1007/978-1-4419-6460-1_11 10.1109/TC.1972.5009071 10.1145/79173.79181 10.1016/0743-7315(91)90085-N |
| ContentType | Journal Article |
| Copyright | 2018 Elsevier B.V. Copyright Elsevier BV Feb 2019 |
| Copyright_xml | – notice: 2018 Elsevier B.V. – notice: Copyright Elsevier BV Feb 2019 |
| DBID | AAYXX CITATION 7SC 7SP 8FD F28 FR3 JQ2 L7M L~C L~D |
| DOI | 10.1016/j.micpro.2018.06.003 |
| DatabaseName | CrossRef Computer and Information Systems Abstracts Electronics & Communications Abstracts Technology Research Database ANTE: Abstracts in New Technology & Engineering Engineering Research Database ProQuest Computer Science Collection Advanced Technologies Database with Aerospace Computer and Information Systems Abstracts Academic Computer and Information Systems Abstracts Professional |
| DatabaseTitle | CrossRef Technology Research Database Computer and Information Systems Abstracts – Academic Electronics & Communications Abstracts ProQuest Computer Science Collection Computer and Information Systems Abstracts Engineering Research Database Advanced Technologies Database with Aerospace ANTE: Abstracts in New Technology & Engineering Computer and Information Systems Abstracts Professional |
| DatabaseTitleList | Technology Research Database |
| DeliveryMethod | fulltext_linktorsrc |
| Discipline | Computer Science |
| EISSN | 1872-9436 |
| EndPage | 142 |
| ExternalDocumentID | 10_1016_j_micpro_2018_06_003 S0141933117302119 |
| GroupedDBID | --K --M -~X .DC .~1 0R~ 123 1B1 1~. 1~5 29M 4.4 457 4G. 5VS 7-5 71M 8P~ 9JN AACTN AAEDT AAEDW AAIAV AAIKJ AAKOC AALRI AAOAW AAQFI AAXUO AAYFN ABBOA ABJNI ABMAC ABXDB ABYKQ ACDAQ ACGFS ACIWK ACNNM ACRLP ACZNC ADBBV ADEZE ADJOM ADMUD ADTZH AEBSH AECPX AEKER AENEX AFKWA AFTJW AGHFR AGUBO AGYEJ AHHHB AHJVU AHZHX AIALX AIEXJ AIKHN AITUG AJBFU AJOXV ALMA_UNASSIGNED_HOLDINGS AMFUW AMRAJ AOUOD AXJTR BJAXD BKOJK BLXMC CS3 DU5 EBS EFJIC EFLBG EJD EO8 EO9 EP2 EP3 F5P FDB FEDTE FGOYB FIRID FNPLU FYGXN G-2 G-Q G8K GBLVA GBOLZ HLZ HVGLF HZ~ IHE J1W JJJVA KOM LG9 LY7 M41 MO0 N9A O-L O9- OAUVE OZT P-8 P-9 P2P PC. PQQKQ Q38 RIG ROL RPZ SBC SDF SDG SDP SES SET SEW SPC SPCBC SST SSV SSZ T5K T9H TN5 UHS WUQ XOL XPP ZMT ~G- 9DU AATTM AAXKI AAYWO AAYXX ABDPE ABWVN ACLOT ACRPL ACVFH ADCNI ADNMO AEIPS AEUPX AFJKZ AFPUW AIGII AIIUN AKBMS AKRWK AKYEP ANKPU APXCP CITATION EFKBS ~HD 7SC 7SP 8FD F28 FR3 JQ2 L7M L~C L~D |
| ID | FETCH-LOGICAL-c283t-a5795e2c4c8613bcbc45f10ebb513dbf903314a018e1f9a1947c75efe59df7a13 |
| ISICitedReferencesCount | 0 |
| ISICitedReferencesURI | http://www.webofscience.com/api/gateway?GWVersion=2&SrcApp=Summon&SrcAuth=ProQuest&DestLinkType=CitingArticles&DestApp=WOS_CPL&KeyUT=000456759600011&url=https%3A%2F%2Fcvtisr.summon.serialssolutions.com%2F%23%21%2Fsearch%3Fho%3Df%26include.ft.matches%3Dt%26l%3Dnull%26q%3D |
| ISSN | 0141-9331 |
| IngestDate | Sun Oct 05 00:11:23 EDT 2025 Sat Nov 29 05:51:35 EST 2025 Fri Feb 23 02:30:03 EST 2024 |
| IsPeerReviewed | true |
| IsScholarly | true |
| Keywords | Massively parallel architecture Parallel processing FPGA Execution model SoC |
| Language | English |
| LinkModel | OpenURL |
| MergedId | FETCHMERGED-LOGICAL-c283t-a5795e2c4c8613bcbc45f10ebb513dbf903314a018e1f9a1947c75efe59df7a13 |
| Notes | ObjectType-Article-1 SourceType-Scholarly Journals-1 ObjectType-Feature-2 content type line 14 |
| PQID | 2178125381 |
| PQPubID | 2045426 |
| PageCount | 15 |
| ParticipantIDs | proquest_journals_2178125381 crossref_primary_10_1016_j_micpro_2018_06_003 elsevier_sciencedirect_doi_10_1016_j_micpro_2018_06_003 |
| PublicationCentury | 2000 |
| PublicationDate | February 2019 2019-02-00 20190201 |
| PublicationDateYYYYMMDD | 2019-02-01 |
| PublicationDate_xml | – month: 02 year: 2019 text: February 2019 |
| PublicationDecade | 2010 |
| PublicationPlace | Kidlington |
| PublicationPlace_xml | – name: Kidlington |
| PublicationTitle | Microprocessors and microsystems |
| PublicationYear | 2019 |
| Publisher | Elsevier B.V Elsevier BV |
| Publisher_xml | – name: Elsevier B.V – name: Elsevier BV |
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| SSID | ssj0005062 |
| Score | 2.1317554 |
| Snippet | This work proposes an execution model for massively parallel systems aiming at ensuring the communications overlap by the computations. This model is named... |
| SourceID | proquest crossref elsevier |
| SourceType | Aggregation Database Index Database Publisher |
| StartPage | 128 |
| SubjectTerms | Computation Computer simulation Configurations Data transfer (computers) Execution model FPGA Massively parallel architecture Order parameters Parallel processing Parallel programming SoC |
| Title | SCAC: Weakly-coupled execution model for massively parallel systems |
| URI | https://dx.doi.org/10.1016/j.micpro.2018.06.003 https://www.proquest.com/docview/2178125381 |
| Volume | 64 |
| WOSCitedRecordID | wos000456759600011&url=https%3A%2F%2Fcvtisr.summon.serialssolutions.com%2F%23%21%2Fsearch%3Fho%3Df%26include.ft.matches%3Dt%26l%3Dnull%26q%3D |
| hasFullText | 1 |
| inHoldings | 1 |
| isFullTextHit | |
| isPrint | |
| journalDatabaseRights | – providerCode: PRVESC databaseName: Elsevier SD Freedom Collection Journals 2021 customDbUrl: eissn: 1872-9436 dateEnd: 99991231 omitProxy: false ssIdentifier: ssj0005062 issn: 0141-9331 databaseCode: AIEXJ dateStart: 19950101 isFulltext: true titleUrlDefault: https://www.sciencedirect.com providerName: Elsevier |
| link | http://cvtisr.summon.serialssolutions.com/2.0.0/link/0/eLvHCXMwtV1Lj9MwELZKlwMX3oiFBfnA1ahO7DjmVpVFy2q7QmIRvUWOO5FYummUtqvyF_jVjGMn6VIhHhKXqHXbPGa-zoxH38wQ8iqWJofE5iyJRpYJnlqmYwCm0dVDGol5MW-mlpyp8_N0NtMfBoPvbS3M9UKVZbrd6uq_qhrXUNmudPYv1N2dFBfwNSodj6h2PP6R4j9OxhO3z_8M5uviG7PLTbXAqBK2YJur-uE3Db3wCiNntHYuwWFqN1RlETo7r3Zj1qnj7FW-oMCN5nGp9iu3tvtdZ7NrRyv1GdITU_Y7fbyP5cbTBqZoXLoPpqZGr7Tu8zpVh7K3gMZl5eF0CqZkZxu7m6BwNVE3yB77lTMhkckRFcEDgDe-qYqYFr4hSmudE7FjXnkoJPeemvu-XHtOwOcjLl-jKFA4jr7ne7SO4t7pdVREx27j7kY42jrX7u4WOYiU1OmQHIzfH89Oe8LQqBlP2915W4jZsAX3r_WrQOcnl9_EMRf3yd2wAaFjD5wHZADlQ3KvHe5Bg61_RCYOR2_oTRTRDkW0QRFFFNEORbRFEQ3IeEw-vTu-mJywMHGDWQwz18xIpSVEVtgUw7zc5lbIgo8gzyWP53mhR_jcwuBDAi-04VooqyQUIPW8UIbHT8iwXJbwlFBpI5CJyg16DGEKYyIo8K1Ae29tYsUhYa14sso3VslaxuFl5sWZOXFmDfEyPiSqlWEWgkMf9GWo9t_88qgVeRb-p6sMd-IY2qK358_--cTPyZ0e70dkuK438ILcttfrL6v6ZYDPD_cYlyA |
| linkProvider | Elsevier |
| openUrl | ctx_ver=Z39.88-2004&ctx_enc=info%3Aofi%2Fenc%3AUTF-8&rfr_id=info%3Asid%2Fsummon.serialssolutions.com&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Ajournal&rft.genre=article&rft.atitle=SCAC%3A+Weakly-coupled+execution+model+for+massively+parallel+systems&rft.jtitle=Microprocessors+and+microsystems&rft.au=Krichene%2C+Hana&rft.au=Baklouti%2C+Mouna&rft.au=Marquet%2C+Philippe&rft.au=Dekeyser%2C+Jean-Luc&rft.date=2019-02-01&rft.pub=Elsevier+B.V&rft.issn=0141-9331&rft.eissn=1872-9436&rft.volume=64&rft.spage=128&rft.epage=142&rft_id=info:doi/10.1016%2Fj.micpro.2018.06.003&rft.externalDocID=S0141933117302119 |
| thumbnail_l | http://covers-cdn.summon.serialssolutions.com/index.aspx?isbn=/lc.gif&issn=0141-9331&client=summon |
| thumbnail_m | http://covers-cdn.summon.serialssolutions.com/index.aspx?isbn=/mc.gif&issn=0141-9331&client=summon |
| thumbnail_s | http://covers-cdn.summon.serialssolutions.com/index.aspx?isbn=/sc.gif&issn=0141-9331&client=summon |